08-01-2018 03:34 PM
I'm currently using Vivado 2017.3.1 and targeting a Virtex 7 part (xc7v2000tflg1925-1). The design takes ~30% of the device. I'm running into a synthesis issue where the synthesis cycle gets to the end and the last entry in the Log is as follows:
INFO: [Common 17-206] Exiting Vivado at Wed Aug 1 16:20:24 2018...
I've been stuck here over 2 hours (as of this message posting). Does anyone have any suggestions on how to resolve this. My laptop information is as follows:
Toshiba Satellite P750
08-01-2018 05:58 PM
08-01-2018 08:00 PM
Are you using GUI project or Tcl script?
Could you post your Synthesis log/report file?
08-01-2018 09:05 PM
Could be an intermittent issue, Can you try restarting your machine and rerun vivado synthesis?
08-01-2018 09:20 PM - edited 08-01-2018 09:22 PM
can you run process monitor and check for any additional files which causes synthesis to stuck?
Is this specific to one project or for all the vivado projects?
08-01-2018 09:25 PM
08-02-2018 11:11 AM
I installed the process monitor you suggested. I ran synthesis and this time it's stuck on the "Loading part: xc7v2000tflg1925-1" phase. I checked the process monitor in real time and notice what I think is strange. It looks like a continuous loop where the same group of files are being created and closed. Specially, under the "Operation" column, there's a "CreateFile-CloseFile" continuous loop. Strange. Thoughts/suggestions?
08-09-2018 07:05 AM
08-10-2018 05:08 AM
1. We need to first understand whether this is a design issue or machine specific issue. Can you try to run the same design on other machine?
2. Can you check .runs/Synth_1 folder and see whether the .dcp file got generated or not? If generated, try to use it for implementation phase as a temporary work around.
3. If you are able to see the same issue on other machines as well, can you share the project archive with us? I will setup an EZmove for file sharing.