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Participant bjackson_ost
Participant
1,290 Views
Registered: ‎03-12-2018

Stuck in synthesis

I'm currently using Vivado 2017.3.1 and targeting a Virtex 7 part (xc7v2000tflg1925-1). The design takes ~30% of the device. I'm running into a synthesis issue where the synthesis cycle gets to the end and the last entry in the Log is as follows:

 

INFO: [Common 17-206] Exiting Vivado at Wed Aug 1 16:20:24 2018...

 

I've been stuck here over 2 hours (as of this message posting). Does anyone have any suggestions on how to resolve this. My laptop information is as follows:

 

Toshiba Satellite P750

Intel Corei7

64 bit

 

 

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11 Replies
Moderator
Moderator
1,269 Views
Registered: ‎11-04-2010

Re: Stuck in synthesis

Hi, @ bjackson_ost ,
Could you try to run synthesis in the Vivado 2018.2?
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Xilinx Employee
Xilinx Employee
1,257 Views
Registered: ‎05-14-2008

Re: Stuck in synthesis

Are you using GUI project or Tcl script?

Could you post your Synthesis log/report file?

 

-vivian

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Moderator
Moderator
1,253 Views
Registered: ‎01-16-2013

Re: Stuck in synthesis

@bjackson_ost

 

Could be an intermittent issue, Can you try restarting your machine and rerun vivado synthesis?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Participant bjackson_ost
Participant
1,246 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@syedz Yes, the issue sometimes goes away when I restart my laptop or restart Vivado.
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Participant bjackson_ost
Participant
1,244 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@ hongh. I'm using the GUI. I'll post the log file should I encounter the same issue.
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Moderator
Moderator
1,242 Views
Registered: ‎01-16-2013

Re: Stuck in synthesis

@bjackson_ost,

 

can you run process monitor and check for any additional files which causes synthesis to stuck?

https://docs.microsoft.com/en-us/sysinternals/downloads/procmon

 

Is this specific to one project or for all the vivado projects?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Participant bjackson_ost
Participant
1,239 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@viviany

I'm using the GUI. I'll post the log if I have the same issue.
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Participant bjackson_ost
Participant
1,237 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@syedz

This happens to this specific design. I'll try that process monitor and let you know. The design I'm working on is a mix of both VHDL and Verilog. Some of the Verilog sub designs have Verilog header files.
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Participant bjackson_ost
Participant
1,183 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@syedz

 

I installed the process monitor you suggested. I ran synthesis and this time it's stuck on the "Loading part: xc7v2000tflg1925-1" phase. I checked the process monitor in real time and notice what I think is strange. It looks like a continuous loop where the same group of files are being created and closed. Specially, under the "Operation" column, there's a "CreateFile-CloseFile" continuous loop. Strange. Thoughts/suggestions?

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Participant bjackson_ost
Participant
776 Views
Registered: ‎03-12-2018

Re: Stuck in synthesis

@syedz@viviany@hongh,

 

It looks like I had to exit Vivado a few times and restart/shutdown my laptop. It's intermittent and I think the size of my design (~30% utilization) contributes.

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Moderator
Moderator
758 Views
Registered: ‎07-21-2014

Re: Stuck in synthesis

@bjackson_ost

 

1. We need to first understand whether this is a design issue or machine specific issue. Can you try to run the same design on other machine?

2. Can you check .runs/Synth_1 folder and see whether the .dcp file got generated or not? If generated, try to use it for implementation phase as a temporary work around.

3. If you are able to see the same issue on other machines as well, can you share the project archive with us? I will setup an EZmove for file sharing.

 

Thanks

Anusheel 

 

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