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Voyager
Voyager
192 Views
Registered: ‎05-30-2018

Synchronous reset isn't taken into account

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Hello,

After implementation I have several warnings like this one:

[DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/logic_v_0/U0/i_logic_vhdl/inst_img_gen/line_buffer0/RAM_reg has an input control pin design_1_i/logic_v_0/U0/i_logic_vhdl/inst_img_gen/line_buffer0/RAM_reg/ADDRARDADDR[10] (net: design_1_i/logic_v_0/U0/i_logic_vhdl/inst_img_gen/line_buffer0/ADDRARDADDR[6]) which is driven by a register (design_1_i/logic_v_0/U0/i_logic_vhdl/inst_img_gen/curr_state_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.

Well, For the moment there are other problems that prevent me from verifying is it true or not.

Nevertheless I tried to solve this problem without checking its impact.

curr_state_reg[i] came for this process:

	FSM_state_reg: process (clk, frame_start1)
	begin
		if frame_start1 = '1' then
			curr_state <= IDLE;
		elsif rising_edge(clk) then
			curr_state <= next_state;
		end if;
	end process;

then I removed frame_start1 from sensitivity list

	FSM_state_reg: process (clk)
	begin
		if frame_start1 = '1' then
			curr_state <= IDLE;
		elsif rising_edge(clk) then
			curr_state <= next_state;
		end if;
	end process;

Then I redid the synthesis.

The warnings didn't disapper.

Then, I took a look at the synthesis and I actually found that curr_state_reg is realized with an asynchronous reset:

asynchronous_reset_at_curr_state.png

Any comments ?

Thanks.

 

 

 

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1 Solution

Accepted Solutions
Contributor
Contributor
172 Views
Registered: ‎10-25-2018

Re: Synchronous reset isn't taken into account

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Your modified code is still using an asynchronous reset. The synthesis compiler can infer a sensitivity list even if you remove an element. The structure you are looking for is:

FSM_state_reg: process (clk)
begin
    if rising_edge(clk) then
        if frame_start1 = '1' then
            curr_state <= IDLE;
        else
            curr_state <= next_state;
        end if;
    end if;    
end process;

 

2 Replies
Contributor
Contributor
173 Views
Registered: ‎10-25-2018

Re: Synchronous reset isn't taken into account

Jump to solution

Your modified code is still using an asynchronous reset. The synthesis compiler can infer a sensitivity list even if you remove an element. The structure you are looking for is:

FSM_state_reg: process (clk)
begin
    if rising_edge(clk) then
        if frame_start1 = '1' then
            curr_state <= IDLE;
        else
            curr_state <= next_state;
        end if;
    end if;    
end process;

 

Voyager
Voyager
161 Views
Registered: ‎05-30-2018

Re: Synchronous reset isn't taken into account

Jump to solution

Of course. Thanks !!!

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