Synplify Pro + Vivado Synthesis : BUFT primitive

[siddadd]

I am using Synplify Pro to generate an edif file which I then use in Vivado for an integrated flow. There are some signals in my Synplify Pro design that are tristated. Vivado seems to be generating black boxes for these signals and I am not sure how to handle it. Below is an example message in my synthesis report.

INFO: [EDIF 20-96] Could not resolve non-primitive black box cell 'BUFT' instantiated as 'data[0]'

Any suggestions how to resolve this black box issue?

Sid

[vemulad]

Hi,

Are you getting errors during Implementation about this BUFT black box?

If Implementation is able to translate this primitive then the INFO message can be ignored. Check how is this BUFT implemented by opening the implemented design? 

Thanks,

Deepika.

[siddadd]

Yes, I am facing errors in implementation.

ERROR: [Opt 31-30] Blackbox data[0] (BUFT) is driving pin CI of primitive cell count_reg[3]_i_2. This blackbox cannot be found in the existing library.

I tried looking up this error and I found this reference http://www.xilinx.com/support/answers/52233.html

Wondering if there is a similar work-around

[vemulad]

Hi,

The AR which you pointed out is a different one. 

I have found a internal CR on this which says that the BUFT is a older primitive and it is not supported in PlanAhead/Vivado.

What is the device you are targetting in vivado? Is the EDIF file generated by targetting the same device?

Thanks,

Deepika.

[siddadd · Accepted solution]

The target device is 7V2000T FHG1761 -1

Yes, I am generating the EDIF targeting the same device

I am going to try and tie my tri-stated signals to zero instead and see if that passes Vivado's PAR

[jsr_broadcom]

I am too getting the same error as below: I am using Synplify pro + vivado (2013.4).

device:xc7v2000t, flg1925, -1.

ERROR: [Opt 31-30] Blackbox debug_bus_6[103] (BUFT) is driving pin D of primitive ce
ll ila_inst/U0/I_TQ0.G_TW[103].U_TQ. This blackbox cannot be found in the existing l
ibrary.
Resolution: Please check the input design and ensure that the specific blackbox modu
le is defined. Once the design is modified, then re-run the Vivado flow.

[mcgett]

As a prior post stated, Vivado does not support translation of BUFTs to AND/OR logic.  You will need to change your code to remove these internal tri-states.

[bassman59]

---

@siddadd wrote:

The target device is 7V2000T FHG1761 -1

Yes, I am generating the EDIF targeting the same device

I am going to try and tie my tri-stated signals to zero instead and see if that passes Vivado's PAR

---

Are you designing with internal (to the FPGA) tristates?

[davidhuo]

It caused by synthesis blackbox , synplify synthesis the tri-port to BUFT which vivado does not support

there are two ways to solve this problem

Method 1:

edit the source file, change the tri-port style from:

/******************************/

data = oe? data_out: 1'bz;

data_in = data;

/******************************/

to :

/***************************************************************/

IOBUF pad_data (.IO(data), .T(oe),I(data_in),O(data_out));

/***************************************************************/

Method 2:

if you don't want to synthesis the design again, you could edit the edif/edf file

seach the BUFT in the edf file , and replace them to  IOBUF

[yashp]

FYI...

if you don't want to synthesis the design again, you could edit the edif/edf file.

--> It's not recommended practice.

Thanks,
Yash