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Contributor
Contributor
186 Views
Registered: ‎08-07-2018

Syntax errors when translating from Verilog to VHDL

Greetings, I tell you that I am trying to translate a project in Verilog to VHDL, the problem is that I am a newbie in Verilog and I have necessarily had to use a translator software, but unfortunately I have only managed to obtain a vhdl code with several syntax errors, of which I have tried to correct a large part, but there are lines in which I can not correct the error. Can someone please help me with these errors? Thanks in advance.
I leave the vhdl code where I mark in red the lines that generate error and in addition to the attached verilog file.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;


entity g1_core_ctrl_stat is
    Port ( 
           i_reset              : in STD_LOGIC;
           i_lclk               : in STD_LOGIC;
           i_cs                 : in STD_LOGIC;
           i_aen_ctrl           : in STD_LOGIC;
           i_cpu_wr_dat         : in STD_LOGIC_VECTOR (15 downto 0);
           i_cpu_addr           : in STD_LOGIC_VECTOR (15 downto 0);
           i_cpu_rnw            : in STD_LOGIC;
           o_cpu_c_s_ta         : in STD_LOGIC;
           o_cpu_c_s_rd_dat     : in STD_LOGIC_VECTOR (15 downto 0);
           i_mmcm_status        : in STD_LOGIC_VECTOR (15 downto 0);
           o_mmcm_en            : in STD_LOGIC_VECTOR (15 downto 0);
           o_device_temp        : in STD_LOGIC_VECTOR (11 downto 0);
           o_timestamp_en       : in STD_LOGIC;
           i_pim1_halfapp_appid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim1_halfapp_revid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim0_halfapp_appid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim0_halfapp_revid : in STD_LOGIC_VECTOR (7 downto 0));
end g1_core_ctrl_stat;

architecture Behavioral of g1_core_ctrl_stat is

-- ////////////////////////////////////////////////////////////////////////
-- Internal Signal and Parameter Declaration
-- ////////////////////////////////////////////////////////////////////////
    SIGNAL RO_G1_CONSTANT           : std_logic_vector(15 DOWNTO 0)     := x"4701";	-- G in ASCII: 0x47, 1 in Hex: 0x01
    SIGNAL G1_CUSTOMERID            : std_logic_vector(15 DOWNTO 0)     := x"7FFF";	
    SIGNAL G1_APPID                 : std_logic_vector(15 DOWNTO 0)     := x"3020";	
    SIGNAL G1_REVID                 : std_logic_vector(31 DOWNTO 0)     := x"00000004";	
    SIGNAL RW_G1_SCRATCHPAD         : std_logic_vector(15 DOWNTO 0);	
    SIGNAL RW_G1_MMCM_EN            : std_logic_vector(15 DOWNTO 0)     := i_mmcm_status;	
    SIGNAL RO_G1_MMCM_STAT          : std_logic_vector(15 DOWNTO 0);	
    SIGNAL RO_G1_DIE_TEMP_ADC_CODE  : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RO_G1_VCCINT_ADC_CODE    : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RO_G1_VCCAUX_ADC_CODE    : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RW_G1_TIMESTAMP_CONTROL  : std_logic_vector(15 DOWNTO 0);
    	
    SIGNAL RO_G1_HALFAPP_PIM1_ID    : to_stdlogicvector(i_pim1_halfapp_appid and i_pim1_halfapp_revid, 16);	
    SIGNAL RO_G1_HALFAPP_PIM0_ID    : to_stdlogicvector(i_pim0_halfapp_appid and i_pim0_halfapp_revid, 16);	
--  The following constant is readable by the host, but has no purpose other than to
--  cause the source code to change slightly. Changing this value is useful when
--  par does not close timing, and all that is needed is a small change to the initial
--  conditions.
    SIGNAL RO_G1_NOP_VALUE          : std_logic_vector(15 DOWNTO 0)     := x"37EE";	
-- ////////////////////////////////////////////////////////////////////
-- Main Code
-- ///////////////////////////////////////////////////////////////////
-- Pass control and status information to I/O
    o_mmcm_en               <=  RW_G1_MMCM_EN;
    o_timestamp_en          <=  RW_G1_TIMESTAMP_CONTROL(0);
    
    SIGNAL aen0             <=  to_stdlogic(i_aen_ctrl AND i_cpu_addr(5) = '0');	
    SIGNAL host_data_regs0  : std_logic_vector(15 DOWNTO 0);	
    SIGNAL ta_regs0         : std_logic;
    
    SIGNAL channel_out  : std_logic_vector(4 DOWNTO 0);	
    SIGNAL sysmon_dout  : std_logic_vector(15 DOWNTO 0);    
    SIGNAL adc_code     : std_logic_vector(15 DOWNTO 0);    
    SIGNAL sysmon_eoc   : std_logic;    
    SIGNAL sysmon_drdy  : std_logic;	
	
BEGIN

    u_g1_ctrl_stat_regs0_x16 : entity work.g1_user_regs_x16
    PORT MAP (
        i_rst       => i_reset,
        i_lclk      => i_lclk,
        i_host_addr => i_cpu_addr(4 DOWNTO 1),
        i_cs        => i_cs,
        i_aen       => aen0,
        i_rnw       => i_cpu_rnw,
        i_host_data => i_cpu_wr_dat,
        o_host_data => host_data_regs0,
        o_ta        => ta_regs0,
        
        i_uclk      => i_lclk,
        
        o_wen_tk    => OPEN,
        
        o_ren_tk    => OPEN,
        
        i_rv0       => RO_G1_CONSTANT,
        i_rv1       => X"0000",
        i_rv2       => X"0000",
        i_rv3       => X"0000",
        i_rv4       => X"0000",
        i_rv5       => X"0000",
        i_rv6       => X"0000",
        i_rv7       => X"0000",
        i_rv8       => X"0000",
        i_rv9       => X"0000",
        i_rv10      => X"0000",
        i_rv11      => X"0000",
        i_rv12      => X"0000",
        i_rv13      => X"0000",
        i_rv14      => X"0000",
        i_rv15      => X"0000",
        i_rd0       => RO_G1_CONSTANT,
        i_rd1       => RW_G1_SCRATCHPAD,
        i_rd2       => G1_CUSTOMERID,
        i_rd3       => G1_APPID,
        i_rd4       => G1_REVID(31 DOWNTO 16),
        i_rd5       => G1_REVID(15 DOWNTO 0),
        i_rd6       => RW_G1_MMCM_EN,
        i_rd7       => RO_G1_MMCM_STAT,
        i_rd8       => RO_G1_DIE_TEMP_ADC_CODE,
        i_rd9       => RO_G1_VCCINT_ADC_CODE,
        i_rd10      => RO_G1_VCCAUX_ADC_CODE,
        i_rd11      => RW_G1_TIMESTAMP_CONTROL,
        i_rd12      => RO_G1_HALFAPP_PIM0_ID,
        i_rd13      => RO_G1_HALFAPP_PIM1_ID,
        i_rd14      => OPEN,
        i_rd15      => RO_G1_NOP_VALUE,
        o_wr0       => OPEN,
        o_wr1       => RW_G1_SCRATCHPAD,
        o_wr2       => OPEN,
        o_wr3       => OPEN,
        o_wr4       => OPEN,
        o_wr5       => OPEN,
        o_wr6       => RW_G1_MMCM_EN,
        o_wr7       => OPEN,
        o_wr8       => OPEN,
        o_wr9       => OPEN,
        o_wr10      => OPEN,
        o_wr11      => RW_G1_TIMESTAMP_CONTROL,
        o_wr12      => OPEN,
        o_wr13      => OPEN,
        o_wr14      => OPEN,
        o_wr15      => OPEN
    );
    o_cpu_c_s_rd_dat    <= host_data_regs0;
    o_cpu_c_s_ta        <= ta_regs0;       	

u_g1_ipcat_xadc : entity work.g1_ipcat_xadc
    PORT MAP (
        --Reset
        reset_in    => i_reset,
        --External FPGA pins
        vp_in       => '0',
        vn_in       => '0',
        --End of conversion signal
        eoc_out     => sysmon_eoc,
        eos_out     => OPEN,
        alarm_out   => OPEN,
        --DRP port
        dclk_in     => i_lclk,
        daddr_in    => B"00" & channel_out,
        den_in      => sysmon_eoc,
        do_out      => sysmon_dout,
        channel_out => channel_out,
        --DRP port - Unused
        dwe_in      => '0',
        di_in       => X"0000",
        busy_out    => OPEN,
        drdy_out    => sysmon_drdy
    );
    adc_code        <= to_stdlogicvector(X"0" AND sysmon_dout(15 DOWNTO 4), 16);

    capture_chan : PROCESS 
    BEGIN
        WAIT UNTIL rising_edge(i_lclk) OR rising_edge(i_reset);
        IF (i_reset /= '0') THEN
            RO_G1_DIE_TEMP_ADC_CODE         <= "0";	
            RO_G1_VCCINT_ADC_CODE           <= "0";	
            RO_G1_VCCAUX_ADC_CODE           <= "0";	
        ELSIF (sysmon_drdy /= '0' and channel_out = "00000") THEN
            RO_G1_DIE_TEMP_ADC_CODE     <= adc_code;	
        ELSIF (sysmon_drdy /= '0' and channel_out = "00001") THEN
            RO_G1_VCCINT_ADC_CODE <= adc_code;	
        ELSIF (sysmon_drdy /= '0' and channel_out = "00010") THEN
            RO_G1_VCCAUX_ADC_CODE <= adc_code;	
        END IF;
    END PROCESS;
    o_device_temp <= to_stdlogicvector(RO_G1_DIE_TEMP_ADC_CODE, 12);    
end Behavioral;

 

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5 Replies
Scholar richardhead
Scholar
153 Views
Registered: ‎08-01-2012

Re: Syntax errors when translating from Verilog to VHDL

Many errors going on here:

1. You cannot do assignments before the "begin" 

2. Signal declarations need a type. They may also be assigned an initial value, but this is not like an "assign" in verilog. These must be done inside the "begin"

3. there is no to_stdlogicvector(int) function, you need to convert via the unsigned type:

some_slv_sig <= std_logic_vector( to_unsigned(some_us_sig, some_slv_sig'length) );

Note: the to_unsigned function call, and std_logic_vector type conversion.

4. the "=" function returns a boolean, not a std_logic. so cannot be anded with a std_logic

5. inputs cannot be assigned a value. (you have a lot of ports pre-pended with o_  I assume these are meant to be outputs, not inputs)

6. "And" is a logic function. & is the concatenate function

 

The syntax checker would have told you all these errors.

 

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Contributor
Contributor
140 Views
Registered: ‎08-07-2018

Re: Syntax errors when translating from Verilog to VHDL

Thank you very much for answering @richardhead ... I told you that I managed to correct the syntax errors as shown

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all; 

entity g1_core_ctrl_status is
    Port ( 
           i_reset              : in STD_LOGIC;
           i_lclk               : in STD_LOGIC;
           i_cs                 : in STD_LOGIC;
           i_aen_ctrl           : in STD_LOGIC;
           i_cpu_wr_dat         : in STD_LOGIC_VECTOR (15 downto 0);
           i_cpu_addr           : in STD_LOGIC_VECTOR (15 downto 0);
           i_cpu_rnw            : in STD_LOGIC;
           o_cpu_c_s_ta         : out STD_LOGIC;
           o_cpu_c_s_rd_dat     : out STD_LOGIC_VECTOR (15 downto 0);
           i_mmcm_status        : in STD_LOGIC_VECTOR (15 downto 0);
           o_mmcm_en            : out STD_LOGIC_VECTOR (15 downto 0);
           o_device_temp        : out STD_LOGIC_VECTOR (11 downto 0);
           o_timestamp_en       : out STD_LOGIC;
           i_pim1_halfapp_appid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim1_halfapp_revid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim0_halfapp_appid : in STD_LOGIC_VECTOR (7 downto 0);
           i_pim0_halfapp_revid : in STD_LOGIC_VECTOR (7 downto 0));
end g1_core_ctrl_status;

architecture Behavioral of g1_core_ctrl_status is

-- ////////////////////////////////////////////////////////////////////////
-- Internal Signal and Parameter Declaration
-- ////////////////////////////////////////////////////////////////////////
    
    constant GND_0 : std_logic := '0';
    constant GND_1 : std_logic_vector(15 DOWNTO 0) := x"0000";
    
    SIGNAL RO_G1_CONSTANT           : std_logic_vector(15 DOWNTO 0)     := x"4701";	-- G in ASCII: 0x47, 1 in Hex: 0x01
    SIGNAL G1_CUSTOMERID            : std_logic_vector(15 DOWNTO 0)     := x"7FFF";	
    SIGNAL G1_APPID                 : std_logic_vector(15 DOWNTO 0)     := x"3020";	
    SIGNAL G1_REVID                 : std_logic_vector(31 DOWNTO 0)     := x"00000004";	
    SIGNAL RW_G1_SCRATCHPAD         : std_logic_vector(15 DOWNTO 0);	
    SIGNAL RW_G1_MMCM_EN            : std_logic_vector(15 DOWNTO 0)     := i_mmcm_status;	
    SIGNAL RO_G1_MMCM_STAT          : std_logic_vector(15 DOWNTO 0);	
    SIGNAL RO_G1_DIE_TEMP_ADC_CODE  : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RO_G1_VCCINT_ADC_CODE    : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RO_G1_VCCAUX_ADC_CODE    : std_logic_vector(15 DOWNTO 0) REGISTER ;	
    SIGNAL RW_G1_TIMESTAMP_CONTROL  : std_logic_vector(15 DOWNTO 0);
    --adc_code        <= (X"0" & sysmon_dout(15 downto 4));
    --assign adc_code = {4'h0, sysmon_dout[15:4]};	
    SIGNAL RO_G1_HALFAPP_PIM1_ID    : std_logic_vector(15 DOWNTO 0) := i_pim1_halfapp_appid & i_pim1_halfapp_revid;	
    SIGNAL RO_G1_HALFAPP_PIM0_ID    : std_logic_vector(15 DOWNTO 0) := i_pim0_halfapp_appid & i_pim0_halfapp_revid; 	
--  The following constant is readable by the host, but has no purpose other than to
--  cause the source code to change slightly. Changing this value is useful when
--  par does not close timing, and all that is needed is a small change to the initial
--  conditions.
    SIGNAL RO_G1_NOP_VALUE          : std_logic_vector(15 DOWNTO 0)     := x"37EE";	
	SIGNAL aen0                 : std_logic;
    SIGNAL host_data_regs0      : std_logic_vector(15 DOWNTO 0);	
    SIGNAL ta_regs0             : std_logic;
    
    SIGNAL channel_out  : std_logic_vector(4 DOWNTO 0);	
    SIGNAL sysmon_dout  : std_logic_vector(15 DOWNTO 0);    
    SIGNAL adc_code     : std_logic_vector(15 DOWNTO 0);    
    SIGNAL sysmon_eoc   : std_logic;    
    SIGNAL sysmon_drdy  : std_logic;	
	
BEGIN
    -- ////////////////////////////////////////////////////////////////////
    -- Main Code
    -- ///////////////////////////////////////////////////////////////////
    -- Pass control and status information to I/O   
    o_mmcm_en               <=  RW_G1_MMCM_EN;
    o_timestamp_en          <=  RW_G1_TIMESTAMP_CONTROL(0);
    aen0                    <=  i_aen_ctrl when (i_cpu_addr(5) = '0')else '0';
    
--    RO_G1_HALFAPP_PIM1_ID(7 downto 0)   <= i_pim1_halfapp_appid & i_pim1_halfapp_revid;
--    RO_G1_HALFAPP_PIM0_ID(7 downto 0)   <= i_pim0_halfapp_appid & i_pim0_halfapp_revid;
    
    u_g1_ctrl_stat_regs0_x16 : g1_user_regs_x16
    PORT MAP (
        i_rst       => i_reset,
        i_lclk      => i_lclk,
        i_host_addr => i_cpu_addr(4 DOWNTO 1),
        i_cs        => i_cs,
        i_aen       => aen0,
        i_rnw       => i_cpu_rnw,
        i_host_data => i_cpu_wr_dat,
        o_host_data => host_data_regs0,
        o_ta        => ta_regs0,
        
        i_uclk      => i_lclk,
        
        o_wen_tk    => OPEN,
        
        o_ren_tk    => OPEN,
        
        i_rv0       => RO_G1_CONSTANT,
        i_rv1       => GND_1,
        i_rv2       => GND_1,
        i_rv3       => GND_1,
        i_rv4       => GND_1,
        i_rv5       => GND_1,
        i_rv6       => GND_1,
        i_rv7       => GND_1,
        i_rv8       => GND_1,
        i_rv9       => GND_1,
        i_rv10      => GND_1,
        i_rv11      => GND_1,
        i_rv12      => GND_1,
        i_rv13      => GND_1,
        i_rv14      => GND_1,
        i_rv15      => GND_1,
        i_rd0       => RO_G1_CONSTANT,
        i_rd1       => RW_G1_SCRATCHPAD,
        i_rd2       => G1_CUSTOMERID,
        i_rd3       => G1_APPID,
        i_rd4       => G1_REVID(31 DOWNTO 16),
        i_rd5       => G1_REVID(15 DOWNTO 0),
        i_rd6       => RW_G1_MMCM_EN,
        i_rd7       => RO_G1_MMCM_STAT,
        i_rd8       => RO_G1_DIE_TEMP_ADC_CODE,
        i_rd9       => RO_G1_VCCINT_ADC_CODE,
        i_rd10      => RO_G1_VCCAUX_ADC_CODE,
        i_rd11      => RW_G1_TIMESTAMP_CONTROL,
        i_rd12      => RO_G1_HALFAPP_PIM0_ID,
        i_rd13      => RO_G1_HALFAPP_PIM1_ID,
        i_rd14      => OPEN,
        i_rd15      => RO_G1_NOP_VALUE,
        o_wr0       => OPEN,
        o_wr1       => RW_G1_SCRATCHPAD,
        o_wr2       => OPEN,
        o_wr3       => OPEN,
        o_wr4       => OPEN,
        o_wr5       => OPEN,
        o_wr6       => RW_G1_MMCM_EN,
        o_wr7       => OPEN,
        o_wr8       => OPEN,
        o_wr9       => OPEN,
        o_wr10      => OPEN,
        o_wr11      => RW_G1_TIMESTAMP_CONTROL,
        o_wr12      => OPEN,
        o_wr13      => OPEN,
        o_wr14      => OPEN,
        o_wr15      => OPEN
    );
    o_cpu_c_s_rd_dat    <= host_data_regs0;
    o_cpu_c_s_ta        <= ta_regs0;       	

u_g1_ipcat_xadc : entity work.g1_ipcat_xadc
    port map (
      -- Reset                                     
      reset_in       => i_reset,      -- in   std_logic
      
      -- External FPGA pins
      vp_in          => GND_0,          -- in   std_logic
      vn_in          => GND_0,          -- in   std_logic
      
      -- End of conversion signal
      eoc_out        => sysmon_eoc,   -- out  std_logic
      eos_out        => open,         -- out  std_logic
      alarm_out      => open,         -- out  std_logic

      -- DRP port
      dclk_in        => i_lclk,       -- in   std_logic
      daddr_in       => B"00" & channel_out,     -- in   std_logic_vector(6 downto 0)
      den_in         => sysmon_eoc,   -- in   std_logic
      do_out         => sysmon_dout,  -- out  std_logic_vector(15 downto 0)
      channel_out    => channel_out,  -- out  std_logic_vector(4 downto 0)

      -- DRP port - Unused
      dwe_in         => GND_0,          -- in   std_logic
      di_in          => GND_1,      -- in   std_logic_vector(15 downto 0)
      busy_out       => open,         -- out  std_logic
      drdy_out       => sysmon_drdy   -- out  std_logic
      );
    adc_code        <= (X"0" & sysmon_dout(15 downto 4));

    CaptureProc : PROCESS (i_lclk,i_reset)
    BEGIN
        IF (i_reset = '1') THEN
            RO_G1_DIE_TEMP_ADC_CODE         <= "0";	
            RO_G1_VCCINT_ADC_CODE           <= "0";	
            RO_G1_VCCAUX_ADC_CODE           <= "0";	
        ELSIF (sysmon_drdy = '1' and channel_out = "00000") THEN
            RO_G1_DIE_TEMP_ADC_CODE     <= adc_code;	
        ELSIF (sysmon_drdy = '1' and channel_out = "00001") THEN
            RO_G1_VCCINT_ADC_CODE <= adc_code;	
        ELSIF (sysmon_drdy = '1' and channel_out = "00010") THEN
            RO_G1_VCCAUX_ADC_CODE <= adc_code;	
        END IF;
    END PROCESS;
    o_device_temp   <= RO_G1_DIE_TEMP_ADC_CODE(11 downto 0);
end Behavioral;

but now I can not synthesize my project due to the error shown in the attached image. It is possible that you can indicate to me the correct way to be able to use a verilog module in my vhdl code.

errorSynth.PNG
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Moderator
Moderator
125 Views
Registered: ‎03-16-2017

Re: Syntax errors when translating from Verilog to VHDL

Hi @cesar182,

Component declaration of g1_user_regs_x16 is missing in your code and hence the error. 

 

compdec.JPG

 

Example of Structrual description of a Half Adder

 

compdec2.JPG

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Contributor
Contributor
101 Views
Registered: ‎08-07-2018

Re: Syntax errors when translating from Verilog to VHDL

I commented that I have already added the modules g1_user_regs_x16 and g1_ipcat_xadc within my hierarchy, I am sorry for not having shown it before. The question I have is that if it is necessary to declare the ports of the modules g1_user_regs_x16 and g1_ipcat_xadc inside g1_core_ctrl_status? I understand that it is enough to add entity work.g1_user_regs_x16 and entity work.g1_ipcat_xadc, but if I have errors in addition to the following observations.

errorSynth.PNG
hierarchy.PNG
g1_user_regs_x16.PNG
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Moderator
Moderator
50 Views
Registered: ‎03-16-2017

Re: Syntax errors when translating from Verilog to VHDL

Hi @cesar182,

 

Can you share the archive project to investigate this issue further?

 

If yes, i will share ezmove ftp test package to send it. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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