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Adventurer
Adventurer
2,621 Views
Registered: ‎01-19-2018

Synth_1 Module not found Block Design v_frmbuf_wr_0

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VIVADO 2017.4 in Windows 64-bit

Vivado is supposed to automatically include the .xci file in the synth_1 run, but it isn't. Out of Contest module runs The error message module "HDMIVDMACSI2_v_frmbuf_wr_0_0_v_frmbuf_wr" not found

Thanks,
Prasanna Daram

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Moderator
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Registered: ‎11-09-2015

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Hi @daram123,

 

In fact I am mixing with the DP IP. It is outside the IP.

 

Anyway, the content of the EDID should be manage by the user depending on the application. Xilinx provide an example but you should use your own EDID.

 

The HDMI IP has an API to modify it: void XV_HdmiRxSs_SetEdidParam

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar jmcclusk
Scholar
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Registered: ‎02-24-2014

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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you are not giving enough context to solve your problem..  Please explain what you are compiling, show the error messages, please.

Don't forget to close a thread when possible by accepting a post as a solution.
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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Please let me know which further information is needed. 

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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Hi @daram123

 

Can you check below few things at your end?

 

1) Make sure the instantiation of HDMIVDMACSI2_v_frmbuf_wr_0_0_v_frmbuf_wr.v module is proper in the HDMIVDMACSI2_v_frmbuf_wr_0_0.v (line 267)

2) Is this HDMIVDMACSI2_v_frmbuf_wr_0_0_v_frmbuf_wr.v is in the non-module section in the design hierarchy? If that is the case then try deleting the complete IP from the design hierarchy and add it again.

3) Lastly try creating project from the scratch again and see if it helps.

 

If above suggestions don't help, please share the design with us to debug this further.

 

Regards

Rohiy

Regards
Rohit
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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Instantiation is proper. Completed the design and added it again.
Error Message persists "module v_frmbuf_wr" not found. VIVADO generated files i couldn't edit.
Design is big enough to share.
Look forward to hear from you.

Thanks & Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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@daram123

 

Is this Xilinx IP or custom IP? In case of Xilinx IP, are you able to open the example design for this core? For custom, can you check for the hierarchy after "Edit in IP Packager".

 

Thanks,

Anusheel

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Adventurer
Adventurer
2,512 Views
Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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This is Xilinx IP Video Frame Buffer Write. There is no example design associated with this IP.

Thanks & Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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@daram123

 

Can you share the exact flow you used? Also, did you try removing and re-adding the IP in case if something went wrong while adding the IP?

In case of Xilinx IPs, the files will be delivered and tool should be able to synthesize it in Global and OOC. Please check for warnings in your project.

 

Thanks,

Anusheel

 

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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Created Block design-> Validate the custom block-> HDL Wrapper-> VIVADO Implementation

IP cores used,
HDMI Rx,
Video Direct Memory Access
Video Write Frame Buffer
MIPI Tx (4 lanes)

Write frame buffer module instatiation says module not found. Line:267. This IP is synthesizing in OCC module run.
There are no other warnings.
Thanks & Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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@daram123

 

Can you share the .bd file here for us to reproduce the issue? 

 

Thanks

Anusheel

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Adventurer
Adventurer
1,803 Views
Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Please find the .bd file for the design as attached.
Thanks & Regards,
Prasanna Daram

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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Hi

registers for EDID values.

Need to write one EDID values for Laptop and another EDID values for camera1 and another EDID values for camera2.

But in FPGA, we do not have the registers for EDID values. Then how can we test with different input HDMI devices?
Here, is this fixed with only a single camera device.

Please confirm.

Regards,
Prasanna Kumar Daram

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Hi @daram123,

 

For the issue with the frame buffer it is really likely to be a windows path issue. Make sure you are using a very short path for your project.

 

For the EDID, this should be another topic but usually in a pass-through design, the HDMI RX is using the EDID from the sink. If you have a RX only design then you might use the xilinx EDID. Note that the management of the EDID should be outsite the HDMI IP and up to the user.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
1,700 Views
Registered: ‎01-19-2018

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Could you elaborate Up "Note that the management of the EDID should be outsite the HDMI IP and up to the user."

Thanks & Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Synth_1 Module not found Block Design v_frmbuf_wr_0

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Hi @daram123,

 

In fact I am mixing with the DP IP. It is outside the IP.

 

Anyway, the content of the EDID should be manage by the user depending on the application. Xilinx provide an example but you should use your own EDID.

 

The HDMI IP has an API to modify it: void XV_HdmiRxSs_SetEdidParam

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**