Yes, please use the "insert" code tag button on the forums and paste text files showing a small example. It's much easier for us to help you that way.
But the short answer, you need to use the "+:", and "-:" range/width selectors in verilog, instead of the variable MSB:LSB that you're doing.
There's been much written about the above - but it's a difficult search term/expression. Dig around some, and let us know if your stilling having trouble. Folks can dig up more pointers for you if neccesary.
Regards,
Mark
