08-24-2020 07:08 AM - edited 08-25-2020 02:10 AM
Above is my program,the following error code appears when I synthesize.
[Synth 8-196] conditional expression could not be resolved to a constant
I use Vivado 2018.3.
08-26-2020 12:10 AM
Can you please attach rtl file here instead of code snippet. It would help to understand issue more clearly.
08-26-2020 04:35 AM
The project you have attached only has top.v RTL file. Please also add RTL file to reproduce the issue you have mentioned.
08-26-2020 07:29 AM
Yes, please use the "insert" code tag button on the forums and paste text files showing a small example. It's much easier for us to help you that way.
But the short answer, you need to use the "+:", and "-:" range/width selectors in verilog, instead of the variable MSB:LSB that you're doing.
There's been much written about the above - but it's a difficult search term/expression. Dig around some, and let us know if your stilling having trouble. Folks can dig up more pointers for you if neccesary.