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Adventurer
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Registered: ‎08-04-2017

[Synth 8-2398]

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I'm trying to migrate a project from ISE 14.7 to Vivado 2017.1.  Following ISE to Vivado Design Suite Migration Guide UG911 v2017.1, I have:

  1. Migrated the ISE Design Suite Design Suite Design to Vivado Design Suite
  2. Migrated the UCF Constraints to XDC by:
    1. Opening the UCFs in PlanAhead 14.7 then using write_xdc to generate a starting point for the .xdc.
    2. Manually reviewing and converting the .xdc that PlanAhead 14.7 wrote

Unfortunately, I got [Synth 8-2398] error when when I Run Synthesis using the original ISE/CG IP that I believe was migrated as part of the above Step 1.  The full log is:

 

*** Running vivado
with args -log icon.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source icon.tcl


****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source icon.tcl -notrace
Command: synth_design -top icon -part xc7k325tffg900-2
Starting synth_design
INFO: [IP_Flow 19-2162] IP 'pcie_7x_v1_11' is locked:
* IP definition '7 Series Integrated Block for PCI Express (1.11)' for IP 'pcie_7x_v1_11' has a newer major version in the IP Catalog.
* Current project part 'xc7k325tffg900-2' and the part 'xc7vx485tffg1761-2' used to customize the IP 'pcie_7x_v1_11' do not match.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t-ffg900'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t-ffg900'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 17524
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 336.793 ; gain = 84.691
---------------------------------------------------------------------------------
WARNING: [Synth 8-5637] invalid to access init_file from inside pure function init_ram [C:/envision/i2i/icon/lib/fpga/src/ram/ramb.vhd:85]
ERROR: [Synth 8-2398] near string "FALSE" ; 10 visible types match here [C:/envision/i2i/icon/i2iDeviceV2_0/fpga/icon_vc707/src/pcie_ctrlr/pcie_wrap.vhd:167]
ERROR: [Synth 8-2398] near string "FALSE" ; 10 visible types match here [C:/envision/i2i/icon/i2iDeviceV2_0/fpga/icon_vc707/src/pcie_ctrlr/pcie_wrap.vhd:168]
INFO: [Synth 8-2810] unit rtl ignored due to previous errors [C:/envision/i2i/icon/i2iDeviceV2_0/fpga/icon_vc707/src/pcie_ctrlr/pcie_wrap.vhd:65]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 379.434 ; gain = 127.332
---------------------------------------------------------------------------------
RTL Elaboration failed
3 Infos, 2 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Aug 4 15:17:43 2017...

 

Note that the lines references are generic parameters in an instantiation of a Verilog module called pcie_7x_v1_11_pipe_clock, which is instantiated from a VHDL wrapper file pcie_wrap.vhd.

 

Unfortunately, the error message is not particularly meaningful to me.  I have tried searching for it and I saw some mentions of it, but none of them seem to applicable to fixing my issue:

 

https://www.xilinx.com/support/answers/67815.html is using XPM UltraRAMs, which I am not using.

https://forums.xilinx.com/t5/7-Series-FPGAs/XAPP524-for-Vivado/td-p/460492 and https://forums.xilinx.com/t5/Synthesis/New-Error-with-VHDL-instantiations-while-migrating-form-Vivdao/td-p/656483 suggest the solution is compiling into a library.  I see Sources > Libraries > Design Sources > Verilog > xil_defaultlib > pcie_7x_v1_11_pipe_clock.v listed, so I believe it is being compiled into a library.  pcie_7x_v1_11_pipe.v is before pcie_wrap.vhd in Source > Compile Order > Design Sources.

https://forums.xilinx.com/t5/SDSoC-Development-Environment/ERROR-Runs-36-287-File-does-not-exist-or-is-not-accessible/td-p/727863 mentions long paths, but I do not think my paths are too long.

 

What does the error mean and how do I fix it?

 

Thanks,

Joseph

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Adventurer
Adventurer
7,534 Views
Registered: ‎08-04-2017

The problem was a component is needed since Vivado 2016.1 does not support component/entity from the work library for Verilog modules per https://www.xilinx.com/support/answers/47454.html. I think the [Synth 8-2398] is because Vivado Synthesis is trying to infer the type, but it is a red herring as it should be erroring out about a missing component/entity before trying to determine the generic types.

To figure this out, I commented out the offending lines since they were being explicitly set to the default values, so there was no functional difference. This got past the [Synth 8-2398] errors to the real error:
[Synth 8-5826] no such design unit 'pcie_7x_v1_11_pipe_clock' in library 'work' ["C:/envision/i2i/icon/i2iDeviceV2_0/fpga/icon_vc707/src/pcie_ctrlr/pcie_wrap.vhd":163]

The above error is also confusing, since it seems like the is there is no work library as Vivado has switched to xil_defaultlib per https://www.xilinx.com/support/answers/59980.html. A co-worker informed me that it is possible to use the entity/component from the work library, as work refers to the current library, which is xil_defaultlib. This could probably be made less confusing by making xil_defaultlib show up in Sources > Libraries as "xil_defaultlib (work)".

Then we tested whether Vivado supported using the entity/component from the work library for Verilog and discovered it did not. While this is documented in AR 47454 mentioned above, the AR indicates the error is [Synth-493] which did not match the [Synth 8-2398] error I encountered. I don't know if the error number has changed since the AR was written or if there are multiple error messages that can be generated depending on different situations or what.

 

Note that after adding the component, it was no longer necessary to comment out the lines causing the [Synth 8-2398] errors.

I feel that debugging this could have been made a lot easier with clearer error messages and better documentation. I suggest the following to make it easier to figure this out:

  1. [Synth 8-5826] should be checked/output before [Synth 8-2398] to avoid a red herring.
  2. References to work and xil_defaultlib should reference the other to indicate they are actually the same, such as:
    • "work (xil_defaultlib) in the [Synth 8-5826] error message
    • "xil_defaultlib (work) in Sources > Design Sources > {Verilog/VHDL}
  3. AR 47454 should be updated to include [Synth 8-5826] in addition to [Synth-493]

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Teacher
Teacher
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Registered: ‎03-31-2012

@jchang_endiag try this AR and see if it helps: https://www.xilinx.com/support/answers/57549.html

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Adventurer
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Registered: ‎08-04-2017

@muzaffer, thanks for the suggestion.  I tried that AR, however the lines with the error are for generics, not ports and none of the ports of that module are assigned to constants.  Also, the error is different as the AR refers to ERROR: [VRFC 10-1089], though the message is similar.

 

I've attached the file with the error as well as file for the Verilog module being instantiated to more clearly illustrate the issue.

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Moderator
Moderator
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Registered: ‎05-31-2017

Hi @jchang_endiag,

This might occur when the files are not compiled in the correct library.

Please make sure that the file pcie_7x_v1_11_pipe_clock.v is present in the work library as you have instantiated from the work library in the pcie_wrap.vhd file.

Thanks & Regards,

A.Shameer.

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Adventurer
Adventurer
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Registered: ‎08-04-2017

Hi @shameera

 

Thanks for the reply.  Sorry, that was actually a mistake in the file I uploaded.  I modified it use xil_defaultlib instead of work, but shelved that change before I attached pcie_wrap.vhd in my last post.  Here is the correct pcie_wrap.vhd.  The line numbers actually match up properly now to the string "FALSE".

 

Best Regards,

Joseph

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Highlighted
Adventurer
Adventurer
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Registered: ‎08-04-2017

The problem was a component is needed since Vivado 2016.1 does not support component/entity from the work library for Verilog modules per https://www.xilinx.com/support/answers/47454.html. I think the [Synth 8-2398] is because Vivado Synthesis is trying to infer the type, but it is a red herring as it should be erroring out about a missing component/entity before trying to determine the generic types.

To figure this out, I commented out the offending lines since they were being explicitly set to the default values, so there was no functional difference. This got past the [Synth 8-2398] errors to the real error:
[Synth 8-5826] no such design unit 'pcie_7x_v1_11_pipe_clock' in library 'work' ["C:/envision/i2i/icon/i2iDeviceV2_0/fpga/icon_vc707/src/pcie_ctrlr/pcie_wrap.vhd":163]

The above error is also confusing, since it seems like the is there is no work library as Vivado has switched to xil_defaultlib per https://www.xilinx.com/support/answers/59980.html. A co-worker informed me that it is possible to use the entity/component from the work library, as work refers to the current library, which is xil_defaultlib. This could probably be made less confusing by making xil_defaultlib show up in Sources > Libraries as "xil_defaultlib (work)".

Then we tested whether Vivado supported using the entity/component from the work library for Verilog and discovered it did not. While this is documented in AR 47454 mentioned above, the AR indicates the error is [Synth-493] which did not match the [Synth 8-2398] error I encountered. I don't know if the error number has changed since the AR was written or if there are multiple error messages that can be generated depending on different situations or what.

 

Note that after adding the component, it was no longer necessary to comment out the lines causing the [Synth 8-2398] errors.

I feel that debugging this could have been made a lot easier with clearer error messages and better documentation. I suggest the following to make it easier to figure this out:

  1. [Synth 8-5826] should be checked/output before [Synth 8-2398] to avoid a red herring.
  2. References to work and xil_defaultlib should reference the other to indicate they are actually the same, such as:
    • "work (xil_defaultlib) in the [Synth 8-5826] error message
    • "xil_defaultlib (work) in Sources > Design Sources > {Verilog/VHDL}
  3. AR 47454 should be updated to include [Synth 8-5826] in addition to [Synth-493]

View solution in original post

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Observer
Observer
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Registered: ‎01-17-2018

I had the error Synth 8-2398 in vivado 2018.3 and it went away after doing File -->  Add sources... and adding (again) the sources related to the error.

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