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Observer jancools
Observer
6,669 Views
Registered: ‎09-20-2013

[Synth 8-27] complex assignment not supported

Hi,

 

I have an issue where the assignment I do is not supported:

[Synth 8-27] complex assignment not supported ["R:/Xilinx/Work/Q115/Q115.srcs/sources_1/new/SkewComp.vhd":85]

 

I'm using oversampling together with GTH transceiver and I put 0's in front of the data to compensate for skew. I made a big variable 1664bit  that can contain the 64 effective data bits with oversamplingfactor max of 26 (64*26 = 1664). In simulation my code works perfectly, but synthesis fails.

 

I've attached the VHD file. It fails on the line:

 

TXDATAOVERSAMPLED((i*ofactor + ofactor-1) downto i*ofactor) := (others => '0');

 

Doing:

 

upindex := (i*ofactor + ofactor-1);

lowindex :=  i*ofactor

TXDATAOVERSAMPLED(upindex downto lowindex) := (others => '0');

 

Also does not help.

Is there any smarter way I can do this that synthesizes ? 

 

Thanks in advance

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3 Replies
Xilinx Employee
Xilinx Employee
6,635 Views
Registered: ‎07-01-2010

Re: [Synth 8-27] complex assignment not supported

Hi,

Currently register or array indexing is not supported in the way you have used.You can have the if, else to check the value of the upindex and lowindex and assign a value to the register index.
Example:
If (upindex = 1 and lowindex = 0 ) then
Txdata(1downto o):=0

Regards,
Achutha
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Newbie davidwende
Newbie
5,741 Views
Registered: ‎11-02-2014

Re: [Synth 8-27] complex assignment not supported

I have a similar problem (Synth 8-27) but am unsure how to rewrite it.

Here are the relevant code sections:

 

signal A : std_logic_vector(2047 downto 0);

signal address : std_logic_vector(12 downto 0);

signal B : std_logic_vector(39 downto 0);

 

begin

 

A( conv_integer(address(6 downto 0) & "11111") downto conv_integer(address(6 downto 0) & "00000") ) <= B(31 downto 0);

 

Thanks

David

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Historian
Historian
5,710 Views
Registered: ‎02-25-2008

Re: [Synth 8-27] complex assignment not supported


@davidwende wrote:

I have a similar problem (Synth 8-27) but am unsure how to rewrite it.

Here are the relevant code sections:

 

signal A : std_logic_vector(2047 downto 0);

signal address : std_logic_vector(12 downto 0);

signal B : std_logic_vector(39 downto 0);

 

begin

 

A( conv_integer(address(6 downto 0) & "11111") downto conv_integer(address(6 downto 0) & "00000") ) <= B(31 downto 0);

 


Consider declaring the signals as naturals instead of std_logic_vectors. That makes the conversions go away, plus it makes more sense to the human readers. Oh, yeah, stop using std_logic_arith.

----------------------------Yes, I do this for a living.