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Adventurer
Adventurer
632 Views
Registered: ‎09-10-2019

[Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

A simple latch is defined as a LUT with a loop instead of a proper latch.

 

 

input logic in_a;
logic sop_n;
logic [3:0] a;
// sop_b is defined under an always_ff sequential to a clock
always_latch begin
  if (!sop_n) begin
    a  <= in_a;
  end
end

 

image.png

 

Why?

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Xilinx Employee
Xilinx Employee
629 Views
Registered: ‎05-22-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp ,

Can you please share the complete test case code?

I am not seeing any output defined.

Thanks,

Raj

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

The output of the LUT is the variable `a`.
All the logics are degined as `(* mark_debug="true" *)`.
The variable `a` should be the output.

The simulation with Vivado Simulator shows correct behavior and no warning.
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Xilinx Employee
Xilinx Employee
618 Views
Registered: ‎05-22-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp ,

I did some modification in your test code:

module lat(in_a,a, sop_n

);

input logic [3:0] in_a;
input logic sop_n;
output logic [3:0] a;
// sop_b is defined under an always_ff sequential to a clock
always_latch begin
if (!sop_n) begin
a <= in_a;
end
end
endmodule

It is inferring latches then:

lat.PNG

Thanks,

Raj

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Adventurer
Adventurer
594 Views
Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

@rshekhaw  , moving the output `a` to an internal signal:

 

 

 

module lat(in_a, sop_n);
input logic [3:0] in_a;
input logic sop_n;
(* mark_debug="true" *) logic [3:0] a;

always_latch begin
    if (!sop_n) begin
        a <= in_a;
    end
end
endmodule

 

 

 

 

image.png

The signal's type shouldn't matter, either as output or internal. Some how it does. Am I wrong somewhere?

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Xilinx Employee
Xilinx Employee
586 Views
Registered: ‎05-22-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp ,

can you please elaborate more on your query?

There are some coding guidelines which is mandatory to follow in order to get desired result from synthesis. There is no output defined so it is not expected to have the desired results out of it.

Thank,

Raj

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Adventurer
Adventurer
581 Views
Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

My question:
Why is the latch defined properly as a latch if the latch's Q is defined as an output (= your example),
while it's elaborated as a LUT with a loop that leads to an implementation error if it's an internal signal (=my example)

Where can I find these coding guidelines? Where is it written that using always_latch with internal signals is forbidden?

 

In UG901: There is no mention of the latch's Q needs to be an output.

 

 

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Obviously in this simple example, there is no output.

Nevertheless, in my real project, the signal is connected to the input of a distributed RAM FIFO.
Why does it matter?

In this simple example, it's defined as mark_debug, it should stay unconnected and correctly elaborated.

Where am I wrong?

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

 
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Xilinx Employee
Xilinx Employee
536 Views
Registered: ‎05-22-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp ,

Are you seeing the elaborated schematic or synthesized schematic?

Thanks,

Raj

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Adventurer
Adventurer
528 Views
Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @rshekhaw,

1. Unfortunately I can't provide my real project, I can just try to have a similar small example.

2. For my example using the latch's Q as an internal logic with mark_debug (instead of an output like your example), here is what I see:

 

* Elaborated

image.png

 

* Synthesized

image.png

 

Once my real project compiled, I can provide you a screenshot. The supposed latch's output is connected to ILA core and sequential logic.

That's for me a real problem, it forces me to use a workaround with comb+ff logics instead of a small latch.

 

Regards,

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Here is the real project synthesized logic:

image.png

As you can see, it's connected to a FIFO and to an ILA core.

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Xilinx Employee
Xilinx Employee
466 Views
Registered: ‎06-14-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp ,

 

What @rshekhaw is suggesting is since there is no load(as of now) and application of mark_debug prevents latch inference. This might need a fix.

In the meantime could you please try following:

module lat(in_a, sop_n);
input logic [3:0] in_a;
input logic sop_n;
logic [3:0] a;
(* mark_debug="true" *) logic [3:0] a_mark;

always_latch begin
if (!sop_n) begin
a <= in_a;
end
end
assign a_mark = a;
endmodule

 

Thanks,

Ajay

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @apetley @rshekhaw ,

Your example is pretty much same as if we define `a` as output. The a is optimized away and is replaced by a_mark.

I don't want to fix the example, I want to fix my real project.

As you can see in my previous answer, the latch's Q has two loads, one is the FIFO, the other one is the ILA core and is still inferred as LUT with loopback.

* What are those guidelines @rshekhaw mentioned for an always_latch to be inferred correctly?

* What can I check in my design? The code is literally same as the example, with the output connected to an ILA core and a FIFO.

I'm fine with a LUT using feedback loop to hold the value if that's the way Vivado thinks it's good BUT,

this is a huge issue in the way Xilinx decided to do it. We have to wait for hours for the bitstream generation to be finished to have an error saying I need to add a constraint that is documented nowhere to allow that combinatory loop. And then wait again for hours. Why a synthesis warning and implementation warning becomes suddenly an error at the bitstream generation?

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

So, it looks like there may be a bug in the tools (and someone could try to file an SR on it) - the tool shouldn't infer the combinatorial feedback (ever). But I suspect that the reason that this bug is being excited is that the code is "unusal" - some code that would normally be optimized out (since it has no output), but is being kept due to a MARK_DEBUG (or other KEEP). The synthesis tool is probably doing something like "I know that this code is going to be optimized out, so I won't bother to infer the latch, but then the MARK_DEBUG makes me keep 'something'"

Others have show that if you add an output to your module, the latch is properly inferred.

But the real question is why does it happen with your "FIFO" there - we need to explore that. How is the "latch" connected to the FIFO? Is the FIFO instantiated or inferred? Are they in the same module or different ones? Is the FIFO RTL code or is it an IP (from the wizard?). Is it compiled "Out-of-context" or "Global".

I suspect there is either something about your code (even with the FIFO) or something about how it is connected to the FIFO that is in some way "odd" that is exciting this bug (for example, maybe the FIFO also doesn't have an output and would normally be optimized out, but the MARK_DEBUG is keeping it too..). That being said, latch based design is almost never used in FPGAs; it is supposed to work, but it isn't terribly surprising that there are more blatant bugs in synthesis when your code is using latches...

Avrum

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Adventurer
Adventurer
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Registered: ‎09-10-2019

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @avrumw,

Thank you for your answer.

1. A paper explains that situation: SystemVerilog Logic Specific Processes for Synthesis‐ Benefits and Proper Usage: http://www.sunburst-design.com/papers/CummingsSNUG2016SV_SVLogicProcs.pdf

2. The FIFO is an instantiated IP (from wizard), Independent clock distributed RAM compiled as "out-of-context".

Emulating a latch using the comb signal when "enable" and using the FF when ~enable; my design simulates correctly and works correctly in hardware. Using a latch here allows me to have a cleaner and more understandable code.

I usually avoid using latch but since that latch is very simple, I thought it'd be a better idea.

3. For the sake of completeness, I'll try to remove the ILA core and the mark_debug to see how it's inferred.

 

Do you have a best-practice logic example to replace a latch?

 

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Xilinx Employee
Xilinx Employee
288 Views
Registered: ‎05-22-2018

Re: [Synth 8-295] found timing loop. => LUT with feedback instead of a latch.

Hi @alexis_jp 

You can try instantiating latch from language template provided in Vivado.

Thanks,

Raj

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