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Claus3
Visitor
Visitor
755 Views
Registered: ‎01-12-2021

[Synth 8-3512] assigned value '2' out of range shouldn't be raised

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Hi,

i've run into this error

   [Synth 8-3512] assigned value '2' out of range

but i don't think it should be there.
I stripped my code down to just produce the error, but the remaining code is useless.

 

----------------------------------------------------------------------------------------------------
library IEEE;           use IEEE.std_logic_1164.all;

entity testcase_Synth_8_3512 is
    port(clk                : in  std_logic;
         request            : in  boolean);
end entity testcase_Synth_8_3512;

----------------------------------------------------------------------------------------------------

architecture behave of testcase_Synth_8_3512 is
    
    constant InBytes_C : natural := 1;
    signal byte_cnt    : natural range 0 to InBytes_C;
        
begin
    
    main_p : process(clk)
    begin
        if rising_edge(clk) then
            if request then
                if byte_cnt = InBytes_C - 1 then
                    byte_cnt <= 0;
                else
                    byte_cnt <= byte_cnt + 1;       -- falsely reports: [Synth 8-3512] assigned value '2' out of range
                end if;
            end if;
        end if;
    end process main_p;

end architecture behave;
----------------------------------------------------------------------------------------------------

 

 

In my opinion, this is legal VHDL code. Simulation agrees with me.

One could argue, that the adder needs a result width of 2 bits, which is more than the signal byte_cnt has.
So this should also happen when InBytes_C is 3, 7, 15, ... then the adder needs an additional result bit.
But I tried with different values of InBytes_C, the only time i get this error is when InBytes_C = 1.

So i don't think this error Synth 8-3512 should be raised here and if there's no other LRM conform explanation, I'd call it a bug.

Regards,
   Claus.

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apetley
Xilinx Employee
Xilinx Employee
588 Views
Registered: ‎06-14-2018

Hi @Claus3 ,

Yes Xilinx do read this though not magically .

This is an issue, will file a ticket to get it fixed.

As @drjohnsmith pointed out this should have not inferred any logic byte_cnt is always resetted to 0 and counter is always in false branch.

Thanks,

Ajay

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6 Replies
bitjockey
Adventurer
Adventurer
640 Views
Registered: ‎03-21-2011

This isn't the right rollover logic.  byte_cnt currently has range 0..1, you should be adding +1 on 0 and using the <= 0 rollover on 1;   Since your integer is range 0..cnt you should roll over on cnt.  if you roll over on cnt-1 then the signal should be 0..cnt-1.  (A counter range 0..NUM_THINGS-1 is a very typical design pattern, otherwise you have one extra possible value than things.)

Remember that byte_cnt is an INGEGER/NATURAL type, not a logic vector, the idea that it has "bits" is not something that happens till later.  It's just an integer with two possible values and you tried to assign it 1+1.  Certainly will not simulate.  *technically* the synthesis is free to use whatever representation it feels minimizes logic (gray, one-hot, etc.) and does not need to be binary.

If this *is* simulating (and the code wasn't 'fixed' between sim and synth) then sim has a bug in it.  It's letting the value 2 be assigned to a subtype of natural that doesn't contain 2.

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richardhead
Scholar
Scholar
620 Views
Registered: ‎08-01-2012

@bitjockey This should simulate just fine. As you said, byte_cnt is 0..1, and the reset occurs when byte_cnt is 0:

if byte_cnt = InBytes_C - 1 then
  byte_cnt <= 0;

byte_cnt will initialise to 0. So in reality, this should synthesise to nothing, as it should be held in reset constantly. There is no way 2 could be assigned to byte_cnt in simulation or synthesis.

This is purely a synthesis bug.

Claus3
Visitor
Visitor
607 Views
Registered: ‎01-12-2021

@bitjockey The code shown does simulate and the simulation is correct.
The simulation would only complain, if it will ever come to the else part with the adder, but this will never happen.
And as you wrote: With using INTEGER/NATURAL, i don't have to care about widths of this signal. Its the job of the synthesis to handle it correctly.
As shown, Vivado Synthesis fails here.


@richardhead I totally agree with you, it is a synthesis bug.
As we have an easy testcase to show the bug, where do we go from here?
Is Xilinx magically reading this and filing an internal bug report, so this gets on the ToDo list for the synthesis guys,
or do we have to inform someone?

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drjohnsmith
Teacher
Teacher
604 Views
Registered: ‎07-09-2009

For my own interest

   I have seen similar in the past , in more than one tool 

InBytes_C - 1

 

where the tools do not cope with constant - number

 I have ended up having two constants 

 

constant InBytes_C : natural := 1;
constant InBytes_m1_c : natural := InBytes_C -1 ;

 

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apetley
Xilinx Employee
Xilinx Employee
589 Views
Registered: ‎06-14-2018

Hi @Claus3 ,

Yes Xilinx do read this though not magically .

This is an issue, will file a ticket to get it fixed.

As @drjohnsmith pointed out this should have not inferred any logic byte_cnt is always resetted to 0 and counter is always in false branch.

Thanks,

Ajay

View solution in original post

apetley
Xilinx Employee
Xilinx Employee
579 Views
Registered: ‎06-14-2018

I meant @richardhead . Not able to edit above comment.

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