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ganson
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Visitor
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Registered: ‎05-06-2021

[Synth 8-549] port width mismatch error during synthesis - Vivado 2020.2

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Hi,

I am in the process of porting a design from Vivado 2017.4 to Vivado 2020.2 and get the following error during synthesis;

[Synth 8-549] port width mismatch for port 'M03_PCIE_CTL_araddr': port width = 31, actual width = 12 ["C:/Projects/sources/common/pci592.vhd":717] & [Synth 8-549] port width mismatch for port 'M03_PCIE_CTL_awaddr': port width = 31, actual width = 12 ["C:/Projects/sources/common/pci592.vhd":721]

I have ZERO idea what this error means and I went looking in the vhd code for that name and found some places however the information on the lines does not give me a clue as to what I should do.

I've asked the vendor for assistance and they told me "it looks like you updated Vivado." This was not what i had expected nor was it very helpful.

Would someone please explain, in detail, what this error means, explicitly, and where and how should I go about resolving it?

P.S. I made changes that I thought would help however they just caused more similar errors.

Thank you all very much - it is greatly appreciated!

-Gary

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ganson
Visitor
Visitor
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Registered: ‎05-06-2021

I figured it out! There is a port pin in the block diagram called M03_PCIE_CTL. I just double clicked on it to bring up a dialog that let me adjust the address width from 31 to 12. Once I did that and ran synthesis again every one of the errors no longer appeared.

All good now... until the next issue...

View solution in original post

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varunra
Xilinx Employee
Xilinx Employee
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Registered: ‎01-24-2017

hi @ganson ,

Looks like you are doing some port connection, where you are connecting 12 bit to 31 bit. you can check if signal "M03_PCIE_CTL_araddr" is 31 bit and what it is getting connected in your design. Try to matching the width. If that doesn't resolve. you can share the piece of code where the issue is happening we can look and let you know.

 

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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

When migrating versions,  its quite normal for ips to change.  Sometimes this might be changes to the ip interface.  Here,  its possible the width of a port changed  but your component still has the old port width. 

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ganson
Visitor
Visitor
255 Views
Registered: ‎05-06-2021

I figured it out! There is a port pin in the block diagram called M03_PCIE_CTL. I just double clicked on it to bring up a dialog that let me adjust the address width from 31 to 12. Once I did that and ran synthesis again every one of the errors no longer appeared.

All good now... until the next issue...

View solution in original post

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