07-22-2018 07:24 AM
I've planned to make some modifications on Xilinx IP, to add some feature.
I've planned to compile the modified code and package it as new IP, so I'll be able to use it in another project, as part of the block design (system).
The original VHDL file contains all design hierarchies, including top entity.
First, I tried to synthesize the original file.
I got the following synthesizer errors:
[Synth 8-2396] near character '1' ; 3 visible types match here ...
After taking care of all this kind of occurrences, this problem was solved but another one popped up.
[Synth 8-5826] no such design unit 'cdc_sync' in library 'lib_cdc_v1_0_2' ...
I'm not sure what to do.
How can I check if cdc_sync is indeed not compiles to library lib_cdc_v1_0_2?
What do I do next?
Should I expect more synthesizer errors? After all, I'm compiling Xilinx IP, which should be compiled with no errors.
I'm using Vivado 2017.4.
I attached original and modified files. Modified file contains only modifications which were required to solve synthesizer errors.
Modified file does not contain the required modifications, for the new feature.
Thank you in advance.
07-23-2018 09:00 AM
07-22-2018 08:43 AM
Hi, @yonatanz ,
You can use report_compile_order -of [get_ips XX] to know how the IP's source files are compiled（For synthesis）.
Compile the all the source files into the proper lib.
07-22-2018 09:18 AM
First, many thanks for your prompt reply.
I didn't quite understands your instructions.
Where do I find this option report_compile_order ?
On Vivado 2017.4, when I right click the Run Synthesis and choose Synthesis Setting, I see other option, but not this one.
What do I do, when I learn how the IP's source files are compiled?
Which library is the proper library and how do I set the library which the files should be compiled to?
As you may see, below, there are several libraries mentioned in the code.
These are three libraries mentioned in the source code.
How do I set the proper library for each IP?
PRE_SFD_count: entity axi_ethernetlite_v3_0_13.cntr5bit
I_TX_FIFO: entity lib_fifo_v1_0_10.async_fifo_fg
CDC_FIFO_EMPTY: entity lib_cdc_v1_0_2.cdc_sync
07-22-2018 06:03 PM - edited 07-22-2018 06:04 PM
Hi, @yonatanz ,
In your project with the original IP xci, you can run the below command in TCL CONSOLE:
report_compile_order -used_in synthesis -of [get_ips XX]
XX is the name of IP, Ex: axi_ethernetlite_0
You can see no all the source files are compiled into xil_defaultLib
07-23-2018 01:24 AM
Sorry, but I'm not sure I've did exactly the right operation.
I did run the TCL command, as follows: report_compile_order -used_in synthesis -of [get_ips axi_ethernetlite]
The report is totally different than the expected.
Looks like all IP instances are missing.
I've done it twice, with the original and the modified files, each on different project.
See attached the two reports.
What do I do to correct that?
How do I set the compile to the proper library?
What is the proper library for each IP?
Do I have to edit the source code to do that?
Thank you again.
07-23-2018 02:26 AM
07-23-2018 03:55 AM
The original idea was to take the axi_ethernetlite core, modify it and compile it, before packaging it as IP which could be re-used, in the full project.
This is the reason that I created new project for this core only.
Under this project, I found no xci file.
When I run the get_ips command, in this project, I get the message: WARNING: [Coretcl 2-176] No IPs found
What does this means? How can I correct this project, in a way that after successful synthesis, I'll be able to package the core.
On the other hand, when I use the original project, which contains the full design, including this core, it does contain xci file, for each IP.
This project has no synthesis errors.
When I run the report_compile_order -used_in synthesis -of [get_ips axi_ethernetlite] command, in this project, I still get missing instances. See attached report report_compile_order_origin1.txt.
Alternatively, when I run your command report_compile_order -used_in synthesis -of [get_ips axi_ethernetlite_0], I get totally different results. there are no missing instances. See attached report report_compile_order_origin2.txt.
Which is the core which I should refer axi_ethernetlite or axi_ethernetlite_0?
On the last command run, I also found that the report referring to the following source files. Should I use them, in the first project, instead of the single axi_ethernetlite_v3_0_vh_rfs.vhd, which I used till now? Is this what you mean, on saying: "there is not only one source file for the IP"?
Following is the list of source files, listed in the latest report:
Source compile order for 'synthesis' with fileset 'system_axi_ethernetlite_0_0' in source management mode 'All':
Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name
----- ---------------------------------- ----------- --------- ------------------------ ----------- -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 axi_lite_ipif_v3_0_vh_rfs.vhd Synth & Sim VHDL axi_lite_ipif_v3_0_4 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd
2 lib_cdc_v1_0_rfs.vhd Synth & Sim VHDL lib_cdc_v1_0_2 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd
3 lib_bmg_v1_0_rfs.vhd Synth & Sim VHDL lib_bmg_v1_0_10 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/9340/hdl/lib_bmg_v1_0_rfs.vhd
4 lib_fifo_v1_0_rfs.vhd Synth & Sim VHDL lib_fifo_v1_0_10 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/f10a/hdl/lib_fifo_v1_0_rfs.vhd
5 axi_ethernetlite_v3_0_vh_rfs.vhd Synth & Sim VHDL axi_ethernetlite_v3_0_13 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/aa69/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd
6 blk_mem_gen_v8_4_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_4_1 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/67d8/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
7 fifo_generator_v13_2_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_2_1 No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ipshared/5c35/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd
8 system_axi_ethernetlite_0_0.vhd Synth VHDL xil_defaultlib No d:/workfolder2/ulink/RND/Digital/Tag/Scc/phase2/Rc4/Bat_origin/ac701_bist.srcs/sources_1/bd/system/ip/system_axi_ethernetlite_0_0/synth/system_axi_ethernetlite_0_0.vhd
Thank you again.
07-23-2018 07:26 AM
Hi, @yonatanz ,
I know you intend to modify and compile the source code of IP axi_ethernetlite core.
The fact you should know is that the source file of IP axi_ethernetlite core is not only one file “axi_ethernetlite_v3_0_vh_rfs.vhd”.
The IP contains 8 VHDL files and 3 XDC files, they should be packaged together as IP and be re-used in the full design.
To know how to compile these VHDL files, you should run “report_compile_order -used_in synthesis -of [get_ips IP_NAME]” in the original project, which contains the full design, including this core(XCI file)
In your design, the IP NAME is “system_axi_ethernetlite_0_0”, so your command should be:
report_compile_order -used_in synthesis -of [get_ips system_axi_ethernetlite_0_0]
In the printed information, you can know which VHDL file should be compiled into which library.
The content is same as line5041~5064 in your report_compile_order_origin1.txt
Index File Name File_Type Library
1 axi_lite_ipif_v3_0_vh_rfs.vhd VHDL axi_lite_ipif_v3_0_4
2 lib_cdc_v1_0_rfs.vhd VHDL lib_cdc_v1_0_2
3 lib_bmg_v1_0_rfs.vhd VHDL lib_bmg_v1_0_10
4 lib_fifo_v1_0_rfs.vhd VHDL lib_fifo_v1_0_10
5 axi_ethernetlite_v3_0_vh_rfs.vhd VHDL axi_ethernetlite_v3_0_13
6 blk_mem_gen_v8_4_vhsyn_rfs.vhd VHDL blk_mem_gen_v8_4_1
7 fifo_generator_v13_2_vhsyn_rfs.vhd VHDL fifo_generator_v13_2_1
8 system_axi_ethernetlite_0_0.vhd VHDL xil_defaultlib
To synthesize the source file, you should replace your modified file and compile it with the other unmodified 7 VHDL files.
All files should be set the proper library when adding them into your new project for IP packaging.
The picture is the example for lib_cdc_v1_0_rfs.vhd. The other files should also be added in the library shown above.
Hope it helps.
07-23-2018 08:57 AM
Your explanation is so detailed now, so I see no reason to miss anything.
Many thanks for your patience.
07-23-2018 09:00 AM
07-25-2018 05:45 AM
I managed to generate bitstream, for the design that include the modified IP.
My current problem is with the SDK.
After Exporting Hardware (including Bitstream) and launching SDK, I get the following error:
ERROR : (XSDB Server)ERROR: [Hsi 55-1403] .../ac701_bist.sdk/Bootloader_bsp/system.mss line 45 - No IP instance named mb0_Peripherias_axi_ethernetlite_0 present in hardware design.
I guess the problem is the software driver that should be associated to the modified IP.
Since I added some logic, which should not affect the software driver, I'd like to keep using the old software driver.
How do I do that?
07-25-2018 07:38 AM
Hi, @yonatanz ,
Please check whether the below link can work:
I suggest you create a new post in EDK board for further debugging guide if the link cannot help.
07-31-2018 05:51 AM
One moment before I close this thread, I'd like to describe the complete process.
1. Check which are the source files participate in the relevant IP, by running the TCL command, report_compile_order -used_in synthesis -of [get_ips name_of_ip], as described above. In case you don't know the relevant IP name, run the command get_ips.
2. Copy all relevant files, including the XDC files, to another location.
3. Open new project and add all relevant files into this project.
4. Make the necessary modifications, inluding in higher hierarchy system_name_of_ip and any additional ports.
5. Run synthesis to eliminate any syntax errors.
6. Run Create and Package command.
7. In the Indentification step, modify the IP name, location, version and IP details as needed. Note that you may need certain name, in order to keep using the same SW drivers. later, when using this IP, the Vivado may add system_ and other characters to this name.
8. In the Review and Package step, Press Package IP.
1. In the main project, open IP Catalog.
2. In the IP Catalog window, right click and choose Add Repository (or Refresh repository, in case repository was already used).
4. Verify that you see the new IP.
5. In the System Diagram, add the new IP and remove any unnecessary IP.
6. Add new ports, in the diagram, if needed.
7. Allocate addresses to the new IP, in the Address Editor.
8. Right click on system and choose Validate Design.
9. Right click on system and choose Generate Output Products.
10. Right click on system and choose Generate HDL wrapper.
11. Run Generate Bitsream.
12. Run Export Hardware including Bitstream.
13. Run Launch SDK
14. Check that all drivers are shown, under BSP. If needed, regenerate BSP or delete is and create it again.
07-31-2018 07:53 AM
08-19-2018 10:30 AM
I'm still trying to make the modified IP working.
Looking at the system.hdf, in the SDK, shows that I have no defined registers, for my modified IP.
When I browse this system.hdf file, in the original project, I see AXI registers, which I don't find on my SDK project.
Looks like I missed something when I generated the new IP.
I attached screenshot of the system.hdf, of both projects. Look at the axi_ethernetlite core.
I'll appreciate your advise.