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Contributor
Contributor
456 Views
Registered: ‎07-26-2018

[Synth 8-6014] [Synth 8-3331] [Synth 8-3332] Unused sequential element was removed.

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I use vivado 2018.2

I got this warning. I know there are many topic for this thing but it didn't work. 

Also in simulation and elaborated design there weren't this warning. But when i synthesis, vivado give me this warning.

Capture222.JPG

[Synth 8-3332] Sequential element (r2g/temp_blue_reg[7]) is unused and will be removed from module top.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;

entity rgb2grey is
                        Port (  
                               clk      : in std_logic;
                               active_i : in std_logic;
                               active_o : out std_logic;
                               rgb_in   : in  std_logic_vector(23 downto 0);
                               gry_o    : out std_logic_vector(7 downto 0)                             
                             );
end rgb2grey;

architecture Behavioral of rgb2grey is
signal red       : unsigned(7 downto 0):=(others=>'Z');
signal green     : unsigned(7 downto 0):=(others=>'Z');
signal blue      : unsigned(7 downto 0):=(others=>'Z');
signal temp_red  : unsigned(7 downto 0):=(others=>'Z');
signal temp_green: unsigned(7 downto 0):=(others=>'Z');
signal temp_blue : unsigned(7 downto 0):=(others=>'Z');
signal temp_sum  : unsigned(7 downto 0):=(others=>'Z');
signal active1, active2 : std_logic;
BEGIN
    process(clk)
    begin
        if rising_edge(clk) then
            if active_i='1' then
                    active1<=active_i;
                    active2<=active1;
                    
                    temp_red   <= (resize((red*3)/10,8));
                    temp_green <= (resize((green*59)/100,8));
                    temp_blue  <= (resize((blue*11)/100,8));
                    temp_sum   <= temp_red + temp_green + temp_blue;
            else
                active1<='0';
                active2<='0';        
            end if;
            end if;
    end process;              
          
        red   <= unsigned(rgb_in(23 downto 16));
        green <= unsigned(rgb_in(15 downto 8));
        blue  <= unsigned(rgb_in(7 downto 0));
        gry_o <= std_logic_vector(temp_sum);
        active_o<=active2;
        
end Behavioral;

Also

Capture.JPG

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;

entity workgroup is
    port (
        clk              : in  std_logic;
        Fcntrl_active_i  : in  std_logic;
        Fcntrl_rd_en_i   : in std_logic;
        conv_running_o   : out std_logic;
        din_w            : in  std_logic_vector(7 downto 0);
        dout_W           : out std_logic_vector(7 downto 0)
    );
end workgroup;

architecture rtl of workgroup is
        
   
    component convolution2d is
                    port (
                        clk      : in  std_logic;
                        start    : in  std_logic;
                        window   : in  frame9;
                        conv_running    : out std_logic;
                        pixel    : out std_logic_vector(7 downto 0)
                    );
    end component;


    signal r1, r2 : frame_type(0 to 7) := (others => (others => 'Z'));
    signal r3: frame_type(0 to 7) := (others => (others => 'Z'));
    signal running2 : std_logic:='0';
    signal cnt_col : natural := 0;
    signal col : integer:=7;
    signal pixcounter : integer:=1;
    signal conv_window : frame9;
    
     type state_type is (st_idle, st_r3,st_r2, st_conv);
     signal  state : state_type := st_idle;
     
begin
    process(clk)
    begin
        if rising_edge(clk) then  
            running2<='0';
            if Fcntrl_active_i='1' then             

--            if Fcntrl_active_i='0' then
--                state<=st_idle;
--                running<='0';
--            else
                                                                
                case state is
                    when st_idle =>
                        if Fcntrl_rd_en_i='1' then
                            r1<= (others => (others => '0'));
                            pixcounter<=0;
                            state<=st_r2;
                        end if;   
                    when st_r2=>
                        r3<=r3(1 to 7) & din_w;     
                        if pixcounter=8 then
                            r2<=r3;
                            state<=st_r3;
                            pixcounter<=9;
                        else
                            pixcounter<=pixcounter+1;    
                        end if;    
                    when st_r3 =>
                        r3<=r3(1 to 7) & din_w;   
                        if pixcounter=16 then
                            running2<='1';
                            r1 <= r1(1 to 7) & r2(0);
                            r2 <= r2(1 to 7) & r3(0);
                            r3 <= r3(1 to 7) & din_w; 
                            conv_window <= r1(0 to 2) & r2(0 to 2) & r3(0 to 2); 
                            cnt_col<=cnt_col+1;
                            state<=st_conv;      
                        elsif pixcounter=15 then
                            running2<='1';
                            conv_window <="00000000" & r1(0 to 1) &  "00000000"   &  r2(0 to 1) &  "00000000" &  r3(1 to 2); -- r3(1 to 2); 0 to 2 için gerekebilir
                            pixcounter<=16;    
                        else
                            pixcounter<=pixcounter+1;
                        end if;          
                    when st_conv=>
                        r1 <= r1(1 to 7) & r2(0);
                        r2 <= r2(1 to 7) & r3(0);
                        r3 <= r3(1 to 7) & din_w;  
                        if(cnt_col<col-1) then
                            running2<='1';
                            conv_window <= r1(0 to 2) & r2(0 to 2) & r3(0 to 2); 
                        end if;
                        if(cnt_col=col) then  
                            running2<='1';
                            conv_window <="00000000" & r1(1 to 2) & "00000000" & r2(1 to 2)  & "00000000" & r3(1 to 2);
                            cnt_col<=0;
                        else
                            cnt_col<=cnt_col+1;    
                        end if;               
                        if cnt_col=col-1 then
                            running2<='1';
                            conv_window <=r1(0 to 1) & "00000000" &   r2(0 to 1) & "00000000"   &  r3(0 to 1) & "00000000" ;
                        end if;      
                end case;   
            end if;           
        end if;
    end process;
          
    c0: convolution2d port map (
        clk=>clk,
        start=>running2, 
        window => conv_window,
        pixel => dout_W,
        conv_running=>conv_running_o
    );


end rtl;

 

For r1,r2,r3

subtype pixel8 is std_logic_vector(7 downto 0); 
type frame_type is array(natural range <>) of pixel8;

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1 Solution

Accepted Solutions
440 Views
Registered: ‎01-22-2015

Re: [Synth 8-6014] Unused sequential element was removed.

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@fpgatr 

In short, you can safely ignore [Synth 8-6014] and [Synth 8-3332] warnings if simulation shows that your VHDL is working properly.  These warnings result from optimization of your VHDL done by synthesis.

In my early FPGA days, I too tried to reason through all the warnings that Xilinx ISE/Vivado synthesis threw at me.  Many, many times I was sure that a synthesis-generated warning pointed to a mistake made by synthesis – but I was always wrong.

So, over the years, I’ve come up with some guidelines for myself:

  1. Xilinx synthesis is always right.
  2. You must resolve critical-warnings and errors reported by synthesis. However, ordinary warnings are not a big deal and can usually be safely ignored.
  3. When writing HDL, clarity and readability are the primary goals - and NOT reducing the number of synthesis warnings.
  4. Use simulation as much as possible. If simulation shows a problem with the HDL then (and only then) do I study the synthesis warnings for clues to the problem.

Cheers,
Mark

7 Replies
441 Views
Registered: ‎01-22-2015

Re: [Synth 8-6014] Unused sequential element was removed.

Jump to solution

@fpgatr 

In short, you can safely ignore [Synth 8-6014] and [Synth 8-3332] warnings if simulation shows that your VHDL is working properly.  These warnings result from optimization of your VHDL done by synthesis.

In my early FPGA days, I too tried to reason through all the warnings that Xilinx ISE/Vivado synthesis threw at me.  Many, many times I was sure that a synthesis-generated warning pointed to a mistake made by synthesis – but I was always wrong.

So, over the years, I’ve come up with some guidelines for myself:

  1. Xilinx synthesis is always right.
  2. You must resolve critical-warnings and errors reported by synthesis. However, ordinary warnings are not a big deal and can usually be safely ignored.
  3. When writing HDL, clarity and readability are the primary goals - and NOT reducing the number of synthesis warnings.
  4. Use simulation as much as possible. If simulation shows a problem with the HDL then (and only then) do I study the synthesis warnings for clues to the problem.

Cheers,
Mark

Contributor
Contributor
427 Views
Registered: ‎07-26-2018

Re: [Synth 8-6014] Unused sequential element was removed.

Jump to solution

markg@prosensing.com wrote:

@fpgatr 

In short, you can safely ignore [Synth 8-6014] and [Synth 8-3332] warnings if simulation shows that your VHDL is working properly.  These warnings result from optimization of your VHDL done by synthesis.

When I looked at the schematic, I saw that the signal was deleted, and this signal (signals) has absolutely significance in my design.

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392 Views
Registered: ‎01-22-2015

Re: [Synth 8-6014] Unused sequential element was removed.

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@fpgatr 

Synthesis is very clever.  When it finds that bits of a signal are never used it will delete them.  Also, if it finds that one signal behaves just like another signal then it will delete one of the signals.

However, if you are sure that the signal being deleted is one that you need, then look at how other VHDL components are connecting signals to the VHDL components that you have shown to us.  Make sure these connecting signals actually go somewhere (eg. to a FPGA port) or are somewhere assigned a value.  Synthesis will delete signals that aren’t connected to anything or aren’t assigned a value.

Running Post Synthesis Functional simulation can help you see what’s going on.  Running Post Synthesis Functional simulation is often as simple as clicking on “Run Post-Synthesis Function Simulation” instead of clicking on “Run Behavioral Simulation”.  However, you may need to simulate the VHDL components that call your rgb2grey and workgroup components rather than simulating rgb2grey and workgroup directly.
post_synth_funct_sim.jpg

Finally, you can force synthesis to not delete signals by using DONT_TOUCH in your VHDL code.  An example of this is:

signal r1, r2 : frame_type(0 to 7) := (others => (others => 'Z'));
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of r1: signal is "TRUE";

Mark

 

 

Contributor
Contributor
384 Views
Registered: ‎07-26-2018

Re: [Synth 8-6014] Unused sequential element was removed.

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markg@prosensing.com  Thank you for all reply. I am  a newbie. I run  Post Synthesis Functional simulation and result is same as behavioral sim. so that means there is no problem?

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Highlighted
358 Views
Registered: ‎01-22-2015

Re: [Synth 8-6014] Unused sequential element was removed.

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@fpgatr 

I run  Post Synthesis Functional simulation and result is same as behavioral sim. so that means there is no problem?
Yes – for now – if Behavioral Simulation showed that the components were working properly.

It sounds like you are starting a large Vivado/VHDL project – and are now writing and testing (via simulation) individual VHDL components that will become part of the project.  This is the correct way to do things.

So, if you are starting a large project and Behavioral Simulation shows that components rgb2grey and workgroup are working properly, then you have done about all you can do at this point.  Also running Post Synthesis Functional Simulation is nice but is usually unnecessary if Behavioral Simulation shows that the components are working properly.

If your project is not yet finished (ie. you have not yet written all the VHDL components and connected them to ports and to each other) then don’t worry too much about what synthesis is doing.  Unconnected things can have far-reaching and hard-to-interpret effects on synthesis.

As your project nears completion, you may want to run Behavioral Simulation on upper-level VHDL components that use rgb2grey and workgroup.  These higher-level simulations will give you additional confidence that rgb2grey and workgroup are working properly.

Also, as your project nears completion, you will be running implementation and receiving results from timing analysis.  Then, changes to rgb2grey and workgroup may be necessary to help your project pass timing analysis.

Good questions!  -keep up the good work.
Mark

Moderator
Moderator
338 Views
Registered: ‎03-16-2017

Re: [Synth 8-6014] Unused sequential element was removed.

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Hi @fpgatr ,

 

Adding further, 

What matters in the end is the desired functionality of your RTL. If you see desired functionality in post synthesis functional simulation, then you do not need to worry about the optimization. 

Else, you can concentrate on the warning messages and apply dont touch attribute to sustain your desired functionality. For more info. on it. check UG901 synthesis user guide.

Regards,
hemangd

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Contributor
Contributor
324 Views
Registered: ‎07-26-2018

Re: [Synth 8-6014] Unused sequential element was removed.

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markg@prosensing.com , thanks for your valuable and full of knowledge reply.

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