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msaideroglu
Observer
Observer
1,124 Views
Registered: ‎11-19-2018

[Synth 8-6038] can not resolve hierarchical name for the item "aw"

I am currently using Vivado 2019.2. When I try to synthesize RTL, getting this error. Can you give me an idea why it is?

(codes are attached)

RTL:

`include "axi/typedef.svh"

module axi_lite_xbar #(
parameter axi_pkg::xbar_cfg_t Cfg = '{NoSlvPorts:2,...},
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type req_t = logic,
parameter type resp_t = logic,
parameter type rule_t = axi_pkg::xbar_rule_64_t,
// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
parameter int unsigned MstIdxWidth = (Cfg.NoMstPorts > 32'd1) ? $clog2(Cfg.NoMstPorts) : 32'd1
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
output resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
output req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o,
input resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i,
input rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i,
input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i
);

.

.

.
`AXI_TYPEDEF_AW_CHAN_T(full_aw_chan_t, addr_t, logic, logic)
`AXI_TYPEDEF_W_CHAN_T(full_w_chan_t, data_t, strb_t, logic)
`AXI_TYPEDEF_B_CHAN_T(full_b_chan_t, logic, logic)
`AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, logic, logic)
`AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, logic, logic)
`AXI_TYPEDEF_REQ_T(full_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t)
`AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t)

// signals from the axi_lite_demuxes, one index more for decode error routing
req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs;
resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps;

// signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID
req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs;
resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps;

.

.

.

addr_decode #(
.NoIndices ( Cfg.NoMstPorts ),
.NoRules ( Cfg.NoAddrRules ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_axi_aw_decode (
.addr_i ( slv_ports_req_i[i].aw.addr ),<<<<<<-----------------------ERROR ROW-------------xxxxxxxxxxxxx----------
.addr_map_i ( addr_map_i ),
.idx_o ( dec_aw ),
.dec_valid_o ( /*not used*/ ),
.dec_error_o ( dec_aw_error ),
.en_default_idx_i ( en_default_mst_port_i[i] ),
.default_idx_i ( default_mst_port_i[i] )
);

Header:

`ifndef AXI_TYPEDEF_SVH_
`define AXI_TYPEDEF_SVH_


`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
axi_pkg::atop_t atop; \
user_t user; \
} aw_chan_t;
`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) \
typedef struct packed { \
data_t data; \
strb_t strb; \
logic last; \
user_t user; \
} w_chan_t;
`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
axi_pkg::resp_t resp; \
user_t user; \
} b_chan_t;
`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
user_t user; \
} ar_chan_t;
`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
data_t data; \
axi_pkg::resp_t resp; \
logic last; \
user_t user; \
} r_chan_t;
`define AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) \
typedef struct packed { \
aw_chan_t aw; \
logic aw_valid; \
w_chan_t w; \
logic w_valid; \
logic b_ready; \
ar_chan_t ar; \
logic ar_valid; \
logic r_ready; \
} req_t;
`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) \
typedef struct packed { \
logic aw_ready; \
logic ar_ready; \
logic w_ready; \
logic b_valid; \
b_chan_t b; \
logic r_valid; \
r_chan_t r; \
} resp_t;
////////////////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////////////////////////
// AXI-Lite (4+Prot) Channel and Request/Response Structs
//
// Usage Example:
// `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_w_t, axi_lite_data_t, axi_lite_strb_t)
// `AXI_LITE_TYPEDEF_B_CHAN_T(axi_lite_b_t)
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t)
// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t)
// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t)
`define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \
typedef struct packed { \
addr_t addr; \
axi_pkg::prot_t prot; \
} aw_chan_lite_t;
`define AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t) \
typedef struct packed { \
data_t data; \
strb_t strb; \
} w_chan_lite_t;
`define AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) \
typedef struct packed { \
axi_pkg::resp_t resp; \
} b_chan_lite_t;
`define AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) \
typedef struct packed { \
addr_t addr; \
axi_pkg::prot_t prot; \
} ar_chan_lite_t;
`define AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) \
typedef struct packed { \
data_t data; \
axi_pkg::resp_t resp; \
} r_chan_lite_t;
`define AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) \
typedef struct packed { \
aw_chan_lite_t aw; \
logic aw_valid; \
w_chan_lite_t w; \
logic w_valid; \
logic b_ready; \
ar_chan_lite_t ar; \
logic ar_valid; \
logic r_ready; \
} req_lite_t;
`define AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) \
typedef struct packed { \
logic aw_ready; \
logic w_ready; \
b_chan_lite_t b; \
logic b_valid; \
logic ar_ready; \
r_chan_lite_t r; \
logic r_valid; \
} resp_lite_t;
////////////////////////////////////////////////////////////////////////////////////////////////////


`endif

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6 Replies
markcurry
Scholar
Scholar
1,080 Views
Registered: ‎09-16-2009

I'm having trouble parsing everything you're doing but it looks like you're using parameter type for your portlists correct?  Any reason you're avoiding SystemVerilog Interfaces?  It's really the proper tool for doing what you're trying to do.

In any event Vivado does support parameter types.  I've used them in my designs - though not to the degree you are.  Structures are supported within Vivado too, as well as array's of them.

So, all the building blocks you're using should be ok in Vivado.

Can you simplify your example?  I'm still missing just where you're overriding the default req_t type of "logic" to whatever structure you're trying to represent.  You must be overriding this parameter type somewhere for things to work. 

Regards,

Mark

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msaideroglu
Observer
Observer
1,020 Views
Registered: ‎11-19-2018

Sorry for late returning. a typedef.svh header is included. The hierarchical names in that header can not be resolved. If I take comment paranthese an error, there appears other errors in same type. Why it can not resolve properly defined structs in a header and package?

Screenshot from 2020-08-31 09-25-25.png

Screenshot from 2020-08-31 09-25-40.png

Screenshot from 2020-08-31 09-26-16.png

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markcurry
Scholar
Scholar
989 Views
Registered: ‎09-16-2009

Please try and simplify your example and post text files - preferably using the code tags within the forum.

Pictures snapshots of code windows in IDE's are not very useful for showing information in a forum.  

I believe I can help - we're doing some very similar things in our code very successfully in Vivado.  Structured Parameter Configs, packages, etc. 

Regards,

Mark

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msaideroglu
Observer
Observer
963 Views
Registered: ‎11-19-2018

Okay. Firstly thanks for  your kindly interest. Let me take from the foundation part I'm trying to sythesize and see th RTL structure of axi_crossbar module that is shared as open source by pulp-platform. All module that I've taken are from axi and common_cells libraries. When I added all sources and set axi_xbar module as top, all sub-modules grayed out unknowingly. So, I started to debug errors.

There are a package file that contains configuration ports in a user defined struct named "axi_pkg.sv" and a header file named "typedef.svh". In axi_pkg, there are a struct for configuration and an enumerated user-defined type that is contained by the previous struct. See below:

 typedef enum logic [9:0] {
    NO_LATENCY    = 10'b000_00_000_00,
    CUT_SLV_AX    = DemuxAw | DemuxAr,
    CUT_MST_AX    = MuxAw | MuxAr,
    CUT_ALL_AX    = DemuxAw | DemuxAr | MuxAw | MuxAr,
    CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR,
    CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR,
    CUT_ALL_PORTS = 10'b111_11_111_11
  } xbar_latency_e;

  /// Configuration for `axi_xbar`.
  typedef struct packed {
    int unsigned   NoSlvPorts;
    int unsigned   NoMstPorts;
    int unsigned   MaxMstTrans;
    int unsigned   MaxSlvTrans;
    bit            FallThrough;
    xbar_latency_e LatencyMode;
    int unsigned   AxiIdWidthSlvPorts;
    int unsigned   AxiIdUsedSlvPorts;
    int unsigned   AxiAddrWidth;
    int unsigned   AxiDataWidth;
    int unsigned   NoAddrRules;
  } xbar_cfg_t;

At below, those configuration and my trial for inititialize values:

module axi_xbar #(
  parameter axi_pkg::xbar_cfg_t Cfg = '0,
module axi_lite_xbar #(
  parameter axi_pkg::xbar_cfg_t Cfg = '{NoSlvPorts:2,NoMstPorts:3,MaxMstTrans:16,MaxSlvTrans:16,FallThrough:1,LatencyMode:NO_LATENCY,AxiIdWidthSlvPorts:32,AxiIdUsedSlvPorts:32,AxiAddrWidth:32,AxiDataWidth:32,NoAddrRules:4},

When axi_pkg is not wildcard imported, NO_LATENCY is not declared error is given, when imported error goes away however "overwriting previous definiton of module axi_pkg" is given as a critical warning. However when observed tcl console, defined values seem to be defined, so it it seems not a big probelm.

Second and big problem is that: these are defined input and outputs which their types defined in typedef.svh.

input  req_t  [Cfg.NoSlvPorts-1:0]                  slv_ports_req_i,
output resp_t [Cfg.NoSlvPorts-1:0]                  slv_ports_resp_o,
output req_t  [Cfg.NoMstPorts-1:0]                  mst_ports_req_o,
input  resp_t [Cfg.NoMstPorts-1:0]                  mst_ports_resp_i,

typedef part:

`ifndef AXI_TYPEDEF_SVH_
`define AXI_TYPEDEF_SVH_

`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)  \
  typedef struct packed {                                       \
    id_t              id;                                       \
    addr_t            addr;                                     \
    axi_pkg::len_t    len;                                      \
    axi_pkg::size_t   size;                                     \
    axi_pkg::burst_t  burst;                                    \
    logic             lock;                                     \
    axi_pkg::cache_t  cache;                                    \
    axi_pkg::prot_t   prot;                                     \
    axi_pkg::qos_t    qos;                                      \
    axi_pkg::region_t region;                                   \
    axi_pkg::atop_t   atop;                                     \
    user_t            user;                                     \
  } aw_chan_t;
`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)  \
  typedef struct packed {                                       \
    data_t data;                                                \
    strb_t strb;                                                \
    logic  last;                                                \
    user_t user;                                                \
  } w_chan_t;
`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)  \
  typedef struct packed {                             \
    id_t            id;                               \
    axi_pkg::resp_t resp;                             \
    user_t          user;                             \
  } b_chan_t;
`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)  \
  typedef struct packed {                                       \
    id_t              id;                                       \
    addr_t            addr;                                     \
    axi_pkg::len_t    len;                                      \
    axi_pkg::size_t   size;                                     \
    axi_pkg::burst_t  burst;                                    \
    logic             lock;                                     \
    axi_pkg::cache_t  cache;                                    \
    axi_pkg::prot_t   prot;                                     \
    axi_pkg::qos_t    qos;                                      \
    axi_pkg::region_t region;                                   \
    user_t            user;                                     \
  } ar_chan_t;
`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)  \
  typedef struct packed {                                     \
    id_t            id;                                       \
    data_t          data;                                     \
    axi_pkg::resp_t resp;                                     \
    logic           last;                                     \
    user_t          user;                                     \
  } r_chan_t;
`define AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)  \
  typedef struct packed {                                         \
    aw_chan_t aw;                                                 \
    logic     aw_valid;                                           \
    w_chan_t  w;                                                  \
    logic     w_valid;                                            \
    logic     b_ready;                                            \
    ar_chan_t ar;                                                 \
    logic     ar_valid;                                           \
    logic     r_ready;                                            \
  } req_t;
`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)  \
  typedef struct packed {                               \
    logic     aw_ready;                                 \
    logic     ar_ready;                                 \
    logic     w_ready;                                  \
    logic     b_valid;                                  \
    b_chan_t  b;                                        \
    logic     r_valid;                                  \
    r_chan_t  r;                                        \
  } resp_t;

 There seems nested defines, and Vivado(2019.2&2020.1) can not resolve those nested define hierarchies. Signal defines in topmodule:

typedef logic [Cfg.AxiAddrWidth-1:0]   addr_t;
  typedef logic [Cfg.AxiDataWidth-1:0]   data_t;
  typedef logic [Cfg.AxiDataWidth/8-1:0] strb_t;
  // to account for the decoding error slave
  typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t;
  // full AXI typedef for the decode error slave, id_t and user_t are logic and will be
  // removed during logic optimization as they are stable
  `AXI_TYPEDEF_AW_CHAN_T(full_aw_chan_t, addr_t, logic, logic)
  `AXI_TYPEDEF_W_CHAN_T(full_w_chan_t, data_t, strb_t, logic)
  `AXI_TYPEDEF_B_CHAN_T(full_b_chan_t, logic, logic)
  `AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, logic, logic)
  `AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, logic, logic)
  `AXI_TYPEDEF_REQ_T(full_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t)
  `AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t)

  // signals from the axi_lite_demuxes, one index more for decode error routing
  req_t  [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs;
  resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps;

  // signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID
  req_t  [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs;
  resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps;

  for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
    logic [MstIdxWidth-1:0] dec_aw,        dec_ar;
    mst_port_idx_t          slv_aw_select, slv_ar_select;
    logic                   dec_aw_error;
    logic                   dec_ar_error;

    full_req_t  decerr_req;
    full_resp_t decerr_resp;

Actual big errors that I am taking examples: "can not resolve for the hierarchical name for the item ...."

i_axi_aw_decode (
      .addr_i           ( slv_ports_req_i[i].aw.addr ),
      .addr_map_i       ( addr_map_i                 ),
      .idx_o            ( dec_aw                     ),
      .dec_valid_o      ( /*not used*/               ),
      .dec_error_o      ( dec_aw_error               ),
      .en_default_idx_i ( en_default_mst_port_i[i]   ),
      .default_idx_i    ( default_mst_port_i[i]      )
    );

slv_ports_reg_i[i].aw.addr can not be resolved. 

Example from a submodule:

 for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_aw
     assign mst_reqs_o[i].aw       = slv_aw_chan.aw;
      assign mst_reqs_o[i].aw_valid = mst_aw_valids[i];
      assign mst_aw_readies[i]      = mst_resps_i[i].aw_ready;
    end

.aw, .aw_ready parts are not resolved. Even today another compiler gave "bad hierarchical name" error for the same rows.

Finally I am getting this error also for the code: (conditional expression could not be resolved to a constant) So this error make me think that configuration initializing also problematic.

 for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux

  

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msaideroglu
Observer
Observer
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Registered: ‎11-19-2018

Could u see my explanation?
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markcurry
Scholar
Scholar
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Registered: ‎09-16-2009

@msaideroglu 

We can see your code.  Speaking for myself however, there's just a bit too much code to wade through.

It appears you have three independent problems.  I suggest making small, complete testcases of each type of error.  Replicating the problem on a small scale can be helpful for you to understand what the tools accept and reject.  Often times, just preparing these small testcases, one can figure out the trouble on your own.  Failing that, you can post the small testcase on the forums, and we can likely help.  I also suggest separating the three failures you are seeing into different forums post to help focus the independent problems.

I will say this, our team are SystemVerilog users within Vivado.  We successfully use many of the features you're trying to use here - including parameter types,  structured parameters, and arrays of all of these.

So, I'm sure there's a path forward for you, but you'll need to do a little more legwork in order for us to help you.

Regards,

Mark

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