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Visitor
Visitor
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Registered: ‎09-23-2020

[Synth 8-639] system function call 'time' not supported ?

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Hello Experts,

I am getting the following warning when I use $time function. 

[Synth 8-639] system function call 'time' not supported.

I am trying to calculate the time when posedge and negedge occurring.

Can you help me to understand this warning message?

My code is given below:

  integer pos_edge;
  integer neg_edge;  
  integer pos_clk_time;
  integer neg_clk_time;  
  integer pulse_width, 
  integer i2c_clk;   
  integer clk_divider = 49999;

always @ (posedge clk_100MHZ) begin
  pos_edge = $time;             
  pos_clk_time = pos_edge; 
end

always @ (negedge clk_100MHZ) begin
  neg_edge = $time;
  neg_clk_time = neg_edge;
  pulse_width = 2 * (neg_clk_time - pos_clk_time);
end

 

Thank you,

Sridhar

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Guide
Guide
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Registered: ‎01-23-2009

What do you expect it to do in synthesis?

The concept of "time" is a purely simulation concept - it assumes that a particular simulation run "starts" at time 0 and then time is counted from that point on.

In an FPGA, there simply is no such concept - a piece of silicon cannot know the current "time" - silicon has flip-flops and combinatorial gates - neither of these have any concept of time. At best, they have the concept of "the passage of edges of a periodic signal" (i.e. a clock), but that is not time - the FPGA cannot tell if those edges are 10ns apart, 10us apart or 10s apart.

So what you are trying to do is fundamentally un-synthesizable. It cannot be converted to FPGA logic, and hence cannot be synthesized. Something like this would be acceptable in an HDL testbench, but definitely not something that is intended to be synthesized.

Avrum

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2 Replies
Moderator
Moderator
358 Views
Registered: ‎07-21-2014

@Sridharan 

As mentioned in the below link on page 238, the $time will be ignored for synthesis. May I know which Vivado version you are using?
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

Thanks
Anusheel 

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Guide
Guide
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Registered: ‎01-23-2009

What do you expect it to do in synthesis?

The concept of "time" is a purely simulation concept - it assumes that a particular simulation run "starts" at time 0 and then time is counted from that point on.

In an FPGA, there simply is no such concept - a piece of silicon cannot know the current "time" - silicon has flip-flops and combinatorial gates - neither of these have any concept of time. At best, they have the concept of "the passage of edges of a periodic signal" (i.e. a clock), but that is not time - the FPGA cannot tell if those edges are 10ns apart, 10us apart or 10s apart.

So what you are trying to do is fundamentally un-synthesizable. It cannot be converted to FPGA logic, and hence cannot be synthesized. Something like this would be acceptable in an HDL testbench, but definitely not something that is intended to be synthesized.

Avrum

View solution in original post