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Contributor
Contributor
519 Views
Registered: ‎06-21-2018

[Synth 8-657] type mismatch for generic 'integer_values' (Mixed language design)

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Hello, 

I have a mixed-language design where I would like to instantiate a VHDL module in a Verilog file. The module has the following definition:

 

 

entity vhdl_module is
generic (
integer_values: work.vectors_and_arrays.integer_vector(7 downto 0) := (0, 0, 0, 0, 0, 0, 0, 0)

);
port(
-- list of ports
);
end vhdl_module;

The vector definition is as simple as follows:

 

type integer_vector     is array (natural range <>) of integer;

 and my instantiation is:

    vhdl_module
      #(
        .integer_values({0,0,0,0,0,0,0,0})       
        )
       I_vhdl_module (
//port connections
        );

 

 

That does not work and trying something like 32'd0 or 1'd0 instead of just 0 did not work any better. What I want to do is simply passing an integer value so I guess the solution must be rather simple, but I did not find it yet. By the way, the VHDL module works fine in a VHDL design where I instantiate it like that:

integer_values => (0, 0, 0, 0, 0, 0, 0, 0)  

So I guess I just need to find the right way to pass an integer value...

Thanks in advance!

Regards, 

javichu

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1 Solution

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Moderator
Moderator
435 Views
Registered: ‎07-21-2014

Re: [Synth 8-657] type mismatch for generic 'integer_values' (Mixed language design)

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@javichu 

Vivado synthesis supports the following VHDL generic types and their Verilog equivalents for mixed language designs: integer, real, string, boolean. -- UG901

The usage looks unsupported. Can you try to modify the generics as normal single integer values and then try to pass it from Verilog module?

Thanks
Anusheel 

3 Replies
Moderator
Moderator
464 Views
Registered: ‎07-21-2014

Re: [Synth 8-657] type mismatch for generic 'integer_values' (Mixed language design)

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@javichu

Can you please check Chapter 9 in below link and make sure the usage is supported:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf

Thanks
Anusheel 

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Contributor
Contributor
449 Views
Registered: ‎06-21-2018

Re: [Synth 8-657] type mismatch for generic 'integer_values' (Mixed language design)

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Hello @anusheel,

thanks for your reply. I did not find anything about integer values, but either found anything about boolean values and that works fine in my design. In that case I use the following definition:

type boolean_vector     is array (natural range <>) of boolean;

and I can pass my paremeters like that without getting any error:

.boolean_values({1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0})

So I don't know what usages are supported... But let's suppose my VHDL module has just one parameter e.g. a single integer value. How could I pass an integer value from Verilog? would anything like ".integer_value(5)" work? Then I could modify the VHDL module to get my integer values separately. I have also read that System Verilog might work better, but I don't know how to define a file or a code section as System Verilog instead of Verilog. Would that make sense? 

Thanks again!

 

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Moderator
Moderator
436 Views
Registered: ‎07-21-2014

Re: [Synth 8-657] type mismatch for generic 'integer_values' (Mixed language design)

Jump to solution

@javichu 

Vivado synthesis supports the following VHDL generic types and their Verilog equivalents for mixed language designs: integer, real, string, boolean. -- UG901

The usage looks unsupported. Can you try to modify the generics as normal single integer values and then try to pass it from Verilog module?

Thanks
Anusheel