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Adventurer
Adventurer
450 Views
Registered: ‎08-10-2017

Synthesis -[Common 17-102] error

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I've recently started encountering the following Synthesis error - 

 

[Common 17-102] Failed writing to file /media/cn1lab005/dataFYP/vivado_projects/fyp/MASTER_AXI_ACC/FullBD_BITGEN_Demo/FullBD_BITGEN_Demo.runs/synth_1/.Xil/Vivado-7941-cn1lab005/dcp101/design_1_smartconnect_2_0.edf.

This error occurs only for this project.
When I opened other projects and ran Synthesis, I did not face any problems. Synthesis completed successfully.

 

What could possibly be the reason for this error ? And how to I resolve it ?

 

 

Thanks 

Regards

Jagannath

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Adventurer
Adventurer
609 Views
Registered: ‎08-10-2017

Re: Synthesis -[Common 17-102] error

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Turns out I had run out of memory. That's why the tool failed to create the file.

 

This project is huge as it contains a block design with a lot of IPs. Probably the tool wanted to create a file of bigger size (compared to other projects whose Synthesis worked).

 

When I deleted some old files and made some space available, Synthesis worked as usual.

 

Use df -h to check how much space is available whenever you encounter errors like failed writing to a file.

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Adventurer
Adventurer
610 Views
Registered: ‎08-10-2017

Re: Synthesis -[Common 17-102] error

Jump to solution

Turns out I had run out of memory. That's why the tool failed to create the file.

 

This project is huge as it contains a block design with a lot of IPs. Probably the tool wanted to create a file of bigger size (compared to other projects whose Synthesis worked).

 

When I deleted some old files and made some space available, Synthesis worked as usual.

 

Use df -h to check how much space is available whenever you encounter errors like failed writing to a file.