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Visitor muleman
Visitor
2,558 Views
Registered: ‎04-06-2017

Synthesis Problem Toplevel Module

Hello folks, 

 

I had a module which reads a text file as an input and do some processing on the content. When I synthesis this module it synthesized fine when I commented the file reading function. However, when I instantiate the same module in my top level module, all the synthesis report is showing is utilization of IO, no LTUs/FFs/BRAMs/DSPs etc. I am not clear on why. 

Here is the my top level module: 

 

entity Synth_Test is
    generic(bitWidth: integer:=16);
    Port ( 
        en: in std_logic;
        clk: in std_logic;
        output1: out STD_LOGIC_VECTOR(bitWidth-1 downto 0)
    );
end Synth_Test;

architecture Behavioral of Synth_Test is

component A is
  Generic(bitWidth: integer:=16; iDim: integer:=40; Dim: integer:=50);
  Port (
            CLK: in STD_LOGIC;
            en: in STD_LOGIC;        
            outData1: out STD_LOGIC_VECTOR(bitWidth-1 downto 0)    

   );
end component;

begin

DUT: A Generic Map(iDim=>28, bitWidth=>16, Dim=>5)
                Port Map(
                  CLK=>CLK,
                  en=>en,        
                  outData1=>output1,

                );

end Behavioral;

Attached is the result of the synthesis result I have for this module. So, why IOs only?

 

synth.jpg
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4 Replies
Moderator
Moderator
2,542 Views
Registered: ‎09-15-2016

Re: Synthesis Problem Toplevel Module

Hi @muleman,

 

I believe the tool will consider the mapping as a black box with no functionality as such and I only see IO's. Let's see what the community has to comment.

 

For those who want to try the code 

outData1=>output1,

remove the comma from port map to avoid synthesis error.

 

Regards,
Prathik
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Visitor muleman
Visitor
2,498 Views
Registered: ‎04-06-2017

Re: Synthesis Problem Toplevel Module

Thanks for you reply.

Meanwhile, what are the scenarios that result in IOs only synthesis report?
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Moderator
Moderator
2,383 Views
Registered: ‎07-21-2014

Re: Synthesis Problem Toplevel Module

@muleman

 

You will need to share the "DUT: A" for us to comment on above results. Above code is only calling the sub-module which looks correct to me.

 

I would suggest to scan the synthesis log file first in order to understand what tool is doing in the synthesis phase, there must me some warning or info in the synthesis log which can explain this behaviour.

 

Also, check the generic value passed into the sub-module and validate that tool is passing the correct value from top-module to lower level. You can find these generic values in synthesis log file.

 

Thanks,
Anusheel
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Visitor muleman
Visitor
2,348 Views
Registered: ‎04-06-2017

Re: Synthesis Problem Toplevel Module

Here I created two simple modules for an easy debug.

entity B is
  Generic(bitWidth: integer:=8; iDim: integer:=3; Dim: integer:=6);
    Port (
        en: in std_logic;
        clk: in std_logic;
        data1: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);    
        data2: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);
        data3: out STD_LOGIC_VECTOR(bitWidth-1 downto 0); 
        data4: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);  
        data5: out STD_LOGIC   
     );
end B;
architecture Behavioral of B is
  component A is
  Generic(bitWidth: integer:=16; iDim: integer:=40; Dim: integer:=50);
  Port (
            CLK: in STD_LOGIC;
            en: in STD_LOGIC;        
            outData1: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);    
            outData2: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);
            outData3: out STD_LOGIC_VECTOR(bitWidth-1 downto 0); 
            outData4: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);   
            outData5: out STD_LOGIC 
   );
end component;
begin
DUT: A Generic Map(iDim=>28, bitWidth=>8, Dim=>5)
                Port Map(
                  CLK=>CLK,
                  en=>en,        
                  outData1=>data1,
                  outData2=>data2,
                  outData3=>data3,
                  outData4=>data4,
                  outData5=>data5
                );
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity A is
  Generic(bitWidth: integer:=16; iDim: integer:=40; Dim: integer:=50);
  Port (
            CLK: in STD_LOGIC;
            en: in STD_LOGIC;        
            outData1: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);    
            outData2: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);
            outData3: out STD_LOGIC_VECTOR(bitWidth-1 downto 0); 
            outData4: out STD_LOGIC_VECTOR(bitWidth-1 downto 0);   
            outData5: out STD_LOGIC 
   );
end entity;
architecture Behavioral of A is
	signal count: STD_LOGIC_VECTOR(bitWidth-1 downto 0);
begin
    Dummy: process(clk) 
        begin
            if(en='1') then
                if(clk'event and clk='1') then
                    outData1<=(others=>'1');
                    outData2<=(others=>'0');
                    outData3<=(others=>'1');
                    outData4<=(others=>'0');
                    outData5<='1'; 
		    count<=std_logic_vector(unsigned(count) + 1);
                end if; 
            end if;
        end process;
end Behavioral;

B being the top level, this will result in a synthesis report with only IOs.  But if I assign the count value to one of the output ports of B every clock cycle, the synthesis works fine.

outData1<=count;

 

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