04-06-2011 03:11 AM
I am a newbie in VHDL and FPGA
I am using FPGA spartan 3AN starter kit, modelsim XE 6.4 and ISE Webpack11.1 for my developement.
As part of my project i am trying to develope a module which will take a bit vector as input and give the position of bits which are set to logic '1' , at each clock transition
for eg if i am giving "1010" as input it will give "01" at first clock and "11" in the next clock.
the code i wrote in VHDL is
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <INP> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
When i checked RTL schematics(attached) it was absolutely not what i wanted . INP , CLK and RST lines were absent in it. instead it has nly buffer.
please tell me what is wrong?? is the problem with my code or synthesis?? please guide me
Thanks in advance
04-06-2011 08:17 AM