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labeeb_ahd
Visitor
Visitor
5,698 Views
Registered: ‎04-06-2011

Synthesis Warning!!!!!!!

Hello 

I am a newbie in VHDL and FPGA

I am using FPGA spartan 3AN starter kit, modelsim XE 6.4 and ISE Webpack11.1 for my developement.

As part of my project i am trying to develope a module which will take a bit vector as input and give the position of bits which are set to logic '1' , at each clock transition

for eg if i am giving "1010"  as input it will give "01" at first clock and "11" in the next clock.

 

 the code i wrote in VHDL is

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_gen is
  generic (n: integer:=8);
    port(
        RST: in std_logic;
        clk: in std_logic;
        INP: in std_logic_vector((n-1) downto 0);
        OUTP: out std_logic_vector(2 downto 0)
       );
end seq_gen;
architecture myarch of seq_gen is
begin
process(RST,CLK,INP)
variable seq: integer range 0 to 8:=0;
begin
if(RST='1') then
  seq := 0;
  OUTP <= "000";
 
 elsif(clk'event and clk = '1') then
    while(seq < 8) loop      
      case INP(seq) is
        when '0'=>
          seq := seq + 1;
        when '1'=>
          OUTP <= conv_std_logic_vector(seq,3);
          seq := seq + 1;          
          EXIT;
        when others =>
          null;
       end case;
    end loop;
  end if;
end process;
end myarch;
I simulated it in model sim and and it was working perfectly. but i synthesized it in ISE XST i got these warning
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

WARNING:Xst:646 - Signal <INP> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

 

When i checked RTL schematics(attached) it was absolutely not what i wanted .  INP , CLK and RST lines were absent in it. instead it has nly buffer.  

 

please tell me what is wrong?? is the problem with my code or synthesis?? please guide me

 

 

Thanks in advance

 

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RTL_SCHM.JPG
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4 Replies
austin
Scholar
Scholar
5,679 Views
Registered: ‎02-27-2008

l,

I suspet your problem is that you have no io pins to connect the signals to defined, so that when the place and route is performed, it finds nothing connected (the warnings) and removes everything that has no connections (as it isn't needed if it isn't connected to anything). Look at an example of how to specify the IO pins (either directly by instantiating the IOBUF in the VHDL, or using the UCF file).

Austin Lesea
Principal Engineer
Xilinx San Jose
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labeeb_ahd
Visitor
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5,659 Views
Registered: ‎04-06-2011

But I have given ucf file
is it any optimization issue in XST?
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labeeb_ahd
Visitor
Visitor
5,658 Views
Registered: ‎04-06-2011

or i shoudnt be using loop inside clock?

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shantesh
Participant
Participant
5,550 Views
Registered: ‎05-11-2010

problem is with your code

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