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Anonymous
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Synthesis based on different languages

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Hello Everyone,

 

I would like to get your suggestions for the following issue. I'm not sure whether any similar topic was created before or not in the Synthesis forum. If it was, sorry or duplication.

As you know, vivado provides the OOC synthesis option to decrease the synthesis time during design phase. But, I'm in a dilemma at this point. When a verilog based IP core was integrated to vhdl based design project, how would vivado perform the synthesis? In other words, which design language will be valid for the OOC synthesis operation?

Is there any benefit to set the project language option to verilog before OOC synthesis process and after the OOC synt. phase for IPs, again adjusting the project language to vhdl and run the overall synthesis in vhdl mode?

In addition, how about the mixed hdl design synthesis case without any IP?

 

Thanks in advance,
Batu

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Moderator
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Registered: ‎07-21-2014

Re: Synthesis based on different languages

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@Anonymous

 

>>When a verilog based IP core was integrated to vhdl based design project, how would vivado perform the synthesis?

Vivado synthesis engine have mixed language support and you should be able to synthesize the design.

 

>> In other words, which design language will be valid for the OOC synthesis operation?

Anusheel: Are you trying to set a RTL file as OOC? If yes, please refer UG901 to know more about this flow. Also, you can set VHDL/Verilog file as OOC and tool will do the job for you.

 

>>Is there any benefit to set the project language option to verilog before OOC synthesis process and after the OOC synt. phase for IPs, again adjusting the project language to vhdl and run the overall synthesis in vhdl mode?

Anusheel: Most of the Xilinx IPs generates both VHDL/Verilog files, if the project language is set to Verilog then tool will generate IP files with .v and same goes with the VHDL as project language. 

 

>>In addition, how about the mixed hdl design synthesis case without any IP?

Anusheel: As mentioned Vivado synthesis supports this flow, you can check the Mixed language support section in the UG901 to get more details.

 

Thanks,
Anusheel
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Registered: ‎09-15-2016

Re: Synthesis based on different languages

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Hi @Anonymous,

 

Please check if the information in this AR#51041 https://www.xilinx.com/support/answers/51041.html is useful.

 

Thanks & Regards,
Prathik
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Re: Synthesis based on different languages

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Hi @Anonymous

When you select the module to run as out-of-context and launch runs, the module is set to the top  module and run the synthesis on the module without creating I/O buffers.The run saves the netlist and saves as stub file. When you run regular synthesis again ooc synthesis insert the stub file into the flow and complile lower level  as black box. Further implementation run insert the lower level netlist in the design.

Refer to below link of UG901 Chapter 8 which talks about Synthesis mixed language support and some do's and dont's you need to follow when instantiating Verilog in the VHDL design and also when instantiating Vhdl in the verilog design.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf#G10.371278

 

 Also for your reference i have attached the archived project  example  in which i have  instantiated a verilog module in the vhdl design and then first running verilog module in ooc mode and finally running regular synthesis for complete design. Hope the example code helps you in understanding how ooc synthesis works for mixed langauge.

 

Regards'

Rohit

 

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Regards
Rohit
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Moderator
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Registered: ‎07-21-2014

Re: Synthesis based on different languages

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@Anonymous

 

>>When a verilog based IP core was integrated to vhdl based design project, how would vivado perform the synthesis?

Vivado synthesis engine have mixed language support and you should be able to synthesize the design.

 

>> In other words, which design language will be valid for the OOC synthesis operation?

Anusheel: Are you trying to set a RTL file as OOC? If yes, please refer UG901 to know more about this flow. Also, you can set VHDL/Verilog file as OOC and tool will do the job for you.

 

>>Is there any benefit to set the project language option to verilog before OOC synthesis process and after the OOC synt. phase for IPs, again adjusting the project language to vhdl and run the overall synthesis in vhdl mode?

Anusheel: Most of the Xilinx IPs generates both VHDL/Verilog files, if the project language is set to Verilog then tool will generate IP files with .v and same goes with the VHDL as project language. 

 

>>In addition, how about the mixed hdl design synthesis case without any IP?

Anusheel: As mentioned Vivado synthesis supports this flow, you can check the Mixed language support section in the UG901 to get more details.

 

Thanks,
Anusheel
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Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
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Anonymous
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Re: Synthesis based on different languages

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@anusheel, @thakurr and @prathikm

 

Thank you very much for your valuable comments and sharings.

 

Best Regards,

Batu

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Re: Synthesis based on different languages

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@Anonymous Please close the thread by marking appropriate post as an answer "Accept as solution" in case it helps to resolve your query.

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