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Visitor
Visitor
3,077 Views
Registered: ‎07-11-2011

Synthesis difference on function and always block

Hi,

 

I figured out that, designed Linear feedbcak shift register (LFSR) produced different synthesis result.

 

When described a small function it produces this synthesis result

 

//-----------------------------

HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 2-bit adder                                           : 1
 8-bit adder                                           : 1
# Registers                                            : 7
 1-bit register                                        : 3
 16-bit register                                       : 1
 2-bit register                                        : 1
 52-bit register                                       : 1
 8-bit register                                        : 1
# Multiplexers                                         : 2
 16-bit 2-to-1 multiplexer                             : 1
 52-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 32
 1-bit xor2                                            : 16
 52-bit xor2                                           : 16

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <>.
The following registers are absorbed into counter <>: 1 register on signal <>.
The following registers are absorbed into counter <>: 1 register on signal <>.
Unit <> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 2-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 71
 Flip-Flops                                            : 71
# Multiplexers                                         : 17
 1-bit 2-to-1 multiplexer                              : 16
 52-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 32
 1-bit xor2                                            : 16
 52-bit xor2                                           : 16

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block , actual ratio is 0.
FlipFlop S_reg_42 has been replicated 1 time(s)
FlipFlop S_reg_44 has been replicated 1 time(s)
FlipFlop S_reg_46 has been replicated 1 time(s)
FlipFlop S_reg_48 has been replicated 1 time(s)
FlipFlop S_reg_49 has been replicated 1 time(s)
FlipFlop S_reg_50 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 87
 Flip-Flops                                            : 87

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         :

Primitive and Black Box Usage:
------------------------------
# BELS                             : 256
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 7
#      LUT2                        : 15
#      LUT3                        : 31
#      LUT4                        : 14
#      LUT5                        : 24
#      LUT6                        : 145
#      MUXCY                       : 7
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 87
#      FD                          : 2
#      FDE                         : 58
#      FDR                         : 3
#      FDRE                        : 24
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 37
#      IBUF                        : 19
#      OBUF                        : 18

Device utilization summary:
---------------------------

Selected Device : 6vsx315tff1156-1


Slice Logic Utilization:
 Number of Slice Registers:              86  out of  393600     0%  
 Number of Slice LUTs:                  239  out of  196800     0%  
    Number used as Logic:               239  out of  196800     0%  

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:    244
   Number with an unused Flip Flop:     158  out of    244    64%  
   Number with an unused LUT:             5  out of    244     2%  
   Number of fully used LUT-FF pairs:    81  out of    244    33%  
   Number of unique control sets:         6

IO Utilization:
 Number of IOs:                          38
 Number of bonded IOBs:                  38  out of    600     6%  
    IOB Flip Flops/Latches:               1

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 87    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 1.876ns (Maximum Frequency: 533.120MHz)
   Minimum input arrival time before clock: 2.505ns
   Maximum output required time after clock: 0.777ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.876ns (frequency: 533.120MHz)
  Total number of paths / destination ports: 723 / 170

 

//--------------------------------------------------------------------

 

 

 

 

 

 

Same block described as always block without change (like just changing head of the block) it produces this result,

 

 

HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 2-bit adder                                           : 1
 8-bit adder                                           : 1
# Registers                                            : 7
 1-bit register                                        : 3
 16-bit register                                       : 1
 2-bit register                                        : 1
 52-bit register                                       : 1
 8-bit register                                        : 1
# Multiplexers                                         : 2
 16-bit 2-to-1 multiplexer                             : 1
 52-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 32
 1-bit xor2                                            : 16
 52-bit xor2                                           : 16

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <>.
The following registers are absorbed into counter <>: 1 register on signal <>.
The following registers are absorbed into counter <>: 1 register on signal <>.
Unit <> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 2-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 71
 Flip-Flops                                            : 71
# Multiplexers                                         : 17
 1-bit 2-to-1 multiplexer                              : 16
 52-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 32
 1-bit xor2                                            : 16
 52-bit xor2                                           : 16

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block , actual ratio is 0.
FlipFlop S_reg_47 has been replicated 1 time(s)
FlipFlop S_reg_48 has been replicated 1 time(s)
FlipFlop S_reg_51 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 84
 Flip-Flops                                            : 84

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         :

Primitive and Black Box Usage:
------------------------------
# BELS                             : 273
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 7
#      LUT2                        : 13
#      LUT3                        : 27
#      LUT4                        : 18
#      LUT5                        : 22
#      LUT6                        : 166
#      MUXCY                       : 7
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 84
#      FD                          : 2
#      FDE                         : 55
#      FDR                         : 3
#      FDRE                        : 24
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 37
#      IBUF                        : 19
#      OBUF                        : 18

Device utilization summary:
---------------------------

Selected Device : 6vsx315tff1156-1


Slice Logic Utilization:
 Number of Slice Registers:              83  out of  393600     0%  
 Number of Slice LUTs:                  256  out of  196800     0%  
    Number used as Logic:               256  out of  196800     0%  

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:    259
   Number with an unused Flip Flop:     176  out of    259    67%  
   Number with an unused LUT:             3  out of    259     1%  
   Number of fully used LUT-FF pairs:    80  out of    259    30%  
   Number of unique control sets:         7

IO Utilization:
 Number of IOs:                          38
 Number of bonded IOBs:                  38  out of    600     6%  
    IOB Flip Flops/Latches:               1

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 84    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 2.395ns (Maximum Frequency: 417.537MHz)
   Minimum input arrival time before clock: 2.812ns
   Maximum output required time after clock: 0.777ns
   Maximum combinational path delay: No path found

 

//-------------------------------------------------------

 

 

 

 

What may be the reason of this difference. .. ?

 

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2 Replies
Highlighted
Scholar
Scholar
3,049 Views
Registered: ‎09-16-2009

Re: Synthesis difference on function and always block

 

Help us out a little here - instead of posting two large report files, and asking "what's the difference", do a little legwork, and tell us what differences specifically concern you?  Number of slices used?  Registers?  Or are you concerned with the timing results? 

 

I'm guessing timing (as a quick eyeball "diff" doesn't show much difference in usage)?  If so, what timing constraints did you apply?

 

Regards,

 

Mark

 

 

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Highlighted
Moderator
Moderator
3,026 Views
Registered: ‎07-21-2014

Re: Synthesis difference on function and always block

@titanic

 

Are you concerned about the utilization difference or the timing results generated by the design with always block? Can you share the RTL code(with function and always block) for us to understand the issue.

 

Thanks,
Anusheel
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