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Participant
Participant
331 Views
Registered: ‎09-28-2018

Synthesis does not proceed for a long time

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I am using Vivado 2016.2.

It looks like the synthesis hasn't progressed for hours.


The elapsed time is about 36 minutes and has not been updated.

Log has not been updated since the display below.

INFO: [Synth 8-256] done synthesizing module 'design_1' (440 # 1) [C: /Work/test/test/test.srcs/sources_1/bd/design_1/hdl/design_1.vhd: 33621]

 

Is there a way to see which part of the design is wrong?

 

Thank you.

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1 Solution

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Scholar
Scholar
304 Views
Registered: ‎08-07-2014

@s3s_elec,

If there is nothing inside the synth log file then difficult.

One reason could be due to improper design constraining or some RTL coding style flaw (RTL syntax is correct in this case). Please re-check these.

If the problem persists even then, then the only way I can think of is removing each module of the design one by one and see when synthesis proceeds. You can isolate the faulty module and analyze it. I know this sounds terrible but don't know any better way.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------

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2 Replies
Scholar
Scholar
305 Views
Registered: ‎08-07-2014

@s3s_elec,

If there is nothing inside the synth log file then difficult.

One reason could be due to improper design constraining or some RTL coding style flaw (RTL syntax is correct in this case). Please re-check these.

If the problem persists even then, then the only way I can think of is removing each module of the design one by one and see when synthesis proceeds. You can isolate the faulty module and analyze it. I know this sounds terrible but don't know any better way.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Participant
Participant
292 Views
Registered: ‎09-28-2018

Hi @dpaul24 ,

Thank you for your reply.

 

I will steadily examine the recently modified modules and design_wrapper.

 

Thank you.

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