cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Explorer
Explorer
1,263 Views
Registered: ‎07-10-2013

Synthesis error: No clock specified in event control

Jump to solution

Using Vivado 2017.4 with simple Verilog code for which behavioral simulation using XSim worked fine, when attempting to Open Elaborated Design, the following error resulted:

 

  • [Synth 8-462] no clock signal specified in event control

for the always@ statement below, which seems to make no sense:

 

initial begin
    RxDataClk = `FALSE;
    RxSquelchClk = `FALSE;
    #15;
    forever begin
        RxDataClk = !RxDataClk;
        #0.801;
        RxSquelchClk = RxDataClk;quarter-period
        #0.801;
        end
    end

always @(posedge RxDataClk) begin: foo0
    if (SystemReset) begin
        RxData <= 20'h00000;
        end //if
    else begin
        RxData <= (RxData + 20'h00001);
        end //else
    end //always foo0

 

0 Kudos
Reply
1 Solution

Accepted Solutions
Explorer
Explorer
1,512 Views
Registered: ‎07-10-2013

Sorry about that, attempted to synthesis the test bench!

 

View solution in original post

0 Kudos
Reply
1 Reply
Explorer
Explorer
1,513 Views
Registered: ‎07-10-2013

Sorry about that, attempted to synthesis the test bench!

 

View solution in original post

0 Kudos
Reply