Synthesis error: No clock specified in event control

[chsdkj]

Using Vivado 2017.4 with simple Verilog code for which behavioral simulation using XSim worked fine, when attempting to Open Elaborated Design, the following error resulted:

• [Synth 8-462] no clock signal specified in event control

for the always@ statement below, which seems to make no sense:

initial begin
    RxDataClk = `FALSE;
    RxSquelchClk = `FALSE;
    #15;
    forever begin
        RxDataClk = !RxDataClk;
        #0.801;
        RxSquelchClk = RxDataClk;quarter-period
        #0.801;
        end
    end

always @(posedge RxDataClk) begin: foo0
    if (SystemReset) begin
        RxData <= 20'h00000;
        end //if
    else begin
        RxData <= (RxData + 20'h00001);
        end //else
    end //always foo0

[chsdkj · Accepted solution]

Sorry about that, attempted to synthesis the test bench!