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Visitor placebo3681
Visitor
2,817 Views
Registered: ‎03-30-2016

Synthesis error when using MARK_DEBUG

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Good day community. I'm having some issues using the attribute MARK_DEBUG and was hoping to get some assistance. I've been reading up the attribute using some of the Xilinx user guides as well as some examples online. I'm using the following code:

 

attribute mark_debug : string;
attribute mark_debug of wr_comp : signal is "TRUE"; 

 

This produces an error stating "<wr_comp> is not declared. The code is located right after "architecture behavior of..." and before the component declarations. After the component declarations, I have the following signal declaration:  

 

signal data_ack, data_error, locked, ram_we, wr_comp: std_logic;

 

I don't fully understand the error since it appears that I do indeed declare the signal wr_comp. Am I missing something here? I'm currently using Vivado 2016.4. Any advice/help, would be greatly appreciated. Thank you in advance!

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1 Solution

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Moderator
Moderator
4,535 Views
Registered: ‎11-09-2015

Re: Synthesis error when using MARK_DEBUG

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Hi @placebo3681,

 

Use attribute mark_debug after the signal declaration and it will work.

 

I think there is a little mistake in the UG901 for VHDL syntax:

"place the proper VHDL attribute syntax before the top-level output port declaration"

 

It seems to be a copy from Verilog syntax but it should be different:

"place the proper VHDL attribute syntax after the top-level output port declaration"

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Moderator
Moderator
4,536 Views
Registered: ‎11-09-2015

Re: Synthesis error when using MARK_DEBUG

Jump to solution

Hi @placebo3681,

 

Use attribute mark_debug after the signal declaration and it will work.

 

I think there is a little mistake in the UG901 for VHDL syntax:

"place the proper VHDL attribute syntax before the top-level output port declaration"

 

It seems to be a copy from Verilog syntax but it should be different:

"place the proper VHDL attribute syntax after the top-level output port declaration"

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor placebo3681
Visitor
2,528 Views
Registered: ‎03-30-2016

Re: Synthesis error when using MARK_DEBUG

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Thank you Florent! Worked as described!

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