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Newbie nroth
Newbie
813 Views
Registered: ‎08-07-2018

Synthesis error with unknown cause: [Synth 8-91] ambiguous clock in event control

I really don't understand this! This error just started appearing on one iteration of my design after I fixed a design bug. The testbench still works fine. I have no idea what could be causing the synthesis error! I have looked on the internet for quite some time trying to understand the error, but I really can't see why the clock here seems ambiguous. My actual job is a deep learning engineer but I am getting a computer engineering degree to learn more about hardware, so please be kind :-)



EDIT: I should mention that this is part of the control unit for an accelerator for a MIPS processor I'm designing

always @(posedge clk, negedge gt, posedge Error) begin

  // Determine next state
  case (state)
    0: state = Go ? 2'd1 : 2'd0;
    1: state = gt ? 2'd2 : 2'd3;
    2: state = (gt && !Error) ? 2'd2 : 2'd3;
    3: state = 0;
  endcase
  
  // Indicate consistency error from compute state, delayed for presentation state
  // A transition will always occur if Error goes high in the compute state (state 2)
  if (state == 2) begin
    Err <= Error;
  end
  if (state == 0) begin
    Err <= 0;
  end
  
  // Set outputs
  case (state)
    0: {en, Done, Load_cnt, Load_reg, present} = 5'b0____0____1____1____0;
    1: {en, Done, Load_cnt, Load_reg, present} = 5'b0____0____0____0____0;
    2: {en, Done, Load_cnt, Load_reg, present} = 5'b1____0____0____1____0;
    3: {en, Done, Load_cnt, Load_reg, present} = 5'b0____1____0____0____1;
  endcase
end
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4 Replies
Moderator
Moderator
801 Views
Registered: ‎02-07-2008

Re: Synthesis error with unknown cause: [Synth 8-91] ambiguous clock in event control

Hi @nroth, there are a couple of related topics, which you may find useful (if you haven't already seen them):

 

https://forums.xilinx.com/t5/7-Series-FPGAs/Synth-8-91-ambiguous-clock-in-event-control/td-p/676245

https://forums.xilinx.com/t5/Welcome-Join/synth-8-91-ambiguous-clk-in-event-control/m-p/724226#M40236

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Newbie nroth
Newbie
784 Views
Registered: ‎08-07-2018

Re: Synthesis error with unknown cause: [Synth 8-91] ambiguous clock in event control

Thanks! I actually did look at both of those pages. I'm sorry to say that they made me even more confused :(

 

I did try mentioning the non-clock signals in if-statements. If I do this, the error still occurs. I also tried removing everything but clk from the sensitivity list but then the design doesn't work properly.

 

I talked to someone I know who does high-level synthesis work, and he told me that my code looked weird but that was all.

 

Again, I really appreciate any help you can give me!

 

Thanks,

Nicholas

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Scholar dpaul24
Scholar
772 Views
Registered: ‎08-07-2014

Re: Synthesis error with unknown cause: [Synth 8-91] ambiguous clock in event control

@nroth,

always @(posedge clk, negedge gt, posedge Error) begin

I think that the part marked in BOLD is causing the problem. Do not use negedge on the sensitivity list.

 

As a workaround, you can have an always block which will detect the falling edge of gt. Thereafter you can use it anywhere in your design.

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Moderator
Moderator
766 Views
Registered: ‎03-16-2017

Re: Synthesis error with unknown cause: [Synth 8-91] ambiguous clock in event control

Hi @nroth,

 

Can you try to add "state" signal with clock edge in sensitivity list and check that you face the same error or not?

 

If the error still present, please provide this source file/testcase to regenerate this issue at our end. In that way we can do an evaluation on it. Because there are multiple root causes of this error. 

 

Regards,

hemangd

Regards,
hemangd

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