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Synthesis error

Newbie
Posts: 2
Registered: ‎06-05-2017

Synthesis error

Using ISE Design Suite 14.7

I have written a code for Full Adder, When I run the synthesis, it shows absolutely no error or warnings but still the synthesis fails.

When I then try to simulate the same code (Synthesis Failed one) it works perfectly fine.
Because of the synthesis failure I am not able to implement the design or get any schematic.

Please Help 

Moderator
Posts: 484
Registered: ‎09-15-2016

Re: Synthesis error

Hi @sudiptaiitkgp

 

Are you seeing same behavior with ISE example design as well? Please check this at your end. Which OS you are using?

Make sure you are using supported OS, please refer below link page 7 for more information on this:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf

 

Regards

Rohit

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Moderator
Posts: 495
Registered: ‎09-15-2016

Re: Synthesis error

Hi @sudiptaiitkgp,

 

What does the log or message console indicate? Try synthesizing any simple user code to check if this issue is reproducing at synthesis stage.

 

Regards,
Prathik
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Moderator
Posts: 1,755
Registered: ‎07-01-2015

Re: Synthesis error

Hi @sudiptaiitkgp,

 

  1. Are you able to synthesize the example designs?
  2. Are you using supported OS? Please go through page-7 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf
  3. Can you try in a different system and see if you are able to synthesize the code.
  4. Also attach the code here for us to check.
Thanks,
Arpan
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Newbie
Posts: 2
Registered: ‎06-05-2017

Re: Synthesis error

I haven't tried for example designs

I am using Windows 10 64 bit. This is in the supported OS

I tried it on another friends computer and it worked fine

Code : 

module FullAdder(
input a, b, cin,
output cout, sum
);

wire a_1, b_1, cin_1;

and and1(a_1, a, b);
and and2(b_1, b, cin);
and and3(cin_1, cin, a);

or or1(cout, a_1, b_1, cin_1);

xor xor1(sum,a,b,cin);


endmodule

Moderator
Posts: 495
Registered: ‎09-15-2016

Re: Synthesis error

Hi @sudiptaiitkgp,

 

This issue should be OS specific, since the full adder module which you shared synthesizes well at my end. I use ISE 14.7 in Windows 7. Moreover, this might be due to instability since Xilinx does not officially support using Windows 8.1 or Windows 10 with ISE Design Suite. This can be confirmed in this document page. no 7, AR#62380 and AR#18419. Since there are no errors or warnings to debug, I believe the best option would be to test in supported OS.

 

Thanks & Regards,
Prathik
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