01-11-2018 10:49 AM - edited 01-11-2018 11:28 AM
Hi, I am getting these errors when running synthesys on rdf0428-zcu106-vcu-trd-2017-2. I have valid licenses and 2017.2 has been able to build zcu106_vcu_multistream project successfully, both projects are provided by Xilinx and have not been modified:
*** Running vivado
with args -log zcu106_vcu_trd_v_mix_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source zcu106_vcu_trd_v_mix_0_0.tcl
****** Vivado v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
**** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
Sourcing tcl script '/opt/Xilinx/Tools/Vivado/2017.2/scripts/Vivado_init.tcl'
478 Beta devices matching pattern found, 143 enabled.
source zcu106_vcu_trd_v_mix_0_0.tcl -notrace
compile_c: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1522.605 ; gain = 0.000 ; free physical = 2608 ; free virtual = 13154
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1522.609 ; gain = 0.000 ; free physical = 2536 ; free virtual = 13082
INFO: [Synth 8-638] synthesizing module 'zcu106_vcu_trd_v_mix_0_0' [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_mix_0_0/synth/zcu106_vcu_trd_v_mix_0_0.v:62]
ERROR: [Synth 8-439] module 'zcu106_vcu_trd_v_mix_0_0_v_mix' not found [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_mix_0_0/synth/zcu106_vcu_trd_v_mix_0_0.v:621]
ERROR: [Synth 8-285] failed synthesizing module 'zcu106_vcu_trd_v_mix_0_0' [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_mix_0_0/synth/zcu106_vcu_trd_v_mix_0_0.v:62]
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1522.609 ; gain = 0.000 ; free physical = 2543 ; free virtual = 13089
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
Other modules failing with similar messages:
- ERROR: [Synth 8-439] module 'zcu106_vcu_trd_v_tpg_1_0_v_tpg' not found [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_tpg_1_0/synth/zcu106_vcu_trd_v_tpg_1_0.v:178]
- ERROR: [Synth 8-439] module 'zcu106_vcu_trd_v_frmbuf_rd_0_0_v_frmbuf_rd' not found [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_frmbuf_rd_0_0/synth/zcu106_vcu_trd_v_frmbuf_rd_0_0.v:261]
- ERROR: [Synth 8-439] module 'zcu106_vcu_trd_v_frmbuf_wr_0_1_v_frmbuf_wr' not found [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_frmbuf_wr_0_1/synth/zcu106_vcu_trd_v_frmbuf_wr_0_1.v:261]
- ERROR: [Synth 8-439] module 'bd_d811_vsc_0_v_vscaler' not found [/home/ridgerun/customers/xilinx/rdf0428-zcu106-vcu-trd-2017-2/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_proc_ss_0_0/bd_0/ip/ip_2/synth/bd_d811_vsc_0.v:178]
Licenses for video mixer, frame buffer and other IPs are working according to license manager, have you seen this kind of errors? Any suggestion on how can it be fixed in order to generate bitstream file?
EDIT: I see that I have: "Zynq UltraScale+ MPSoC Early Access License 2017.1 Devices" could it be that I need 2017.2?
01-11-2018 09:15 PM
As you say that the other zcu106_vcu_x project implements successfully at your end, hence i have the feeling that your 2nd
project has got corrupt. Do you see '?' symbol corresponding to these files in the source hierarchy window? If yes, try deleting those files with '?' symbol and add again. In case you are not able to delete it which happens due to their definition already present in the .xpr. Try editing the .xpr file and remove the definitions permanently from there.
Let me know if i misunderstood anything.
01-12-2018 08:34 AM
As per my experience in video IPs, this still looks like a licensing issue to me.
Could you share a screenshot of you Vivado License Manager.
I am interested in the licenses for the Video IPs (mixer/TPG and frame buffer). Please show the column version limit and host IP match.
01-12-2018 09:48 AM
Yes, currently ZCU106_VCU_Design_package_2017.2.zip build OK, but rdf0428-zcu106-vcu-trd-2017-2 is not building.
I am checking at the hierarchy window but I don't see any '?' please check attached hierarchy-vivado.png I have navigated on the window, but wasn't able to find any '?'
Also the errors are reported at .v files, please check attached error-messages.png I was checking the "zcu106_vcu_trd.xpr" but it doesn't contains .v files on it which are the files that are reporting errors.
Thank you for your time.
01-12-2018 02:15 PM
License manager snapshot attached, I didnt find one for framebuffer write or read. I agree with you on the license comment I think I should focus on the licenses.
02-01-2018 11:46 AM
02-02-2018 07:13 AM
You might need to use the vivado from SDx instaed of vivado as standalone. Prior to 2017.4, the 2 vivado had a differents version.
02-02-2018 07:25 AM
moved to Vivado 2017.3 got licenses for 2017.3 and rdf0428 for 2017.3, the reported errors doesn't happens anymore. Now I am getting another error:
[Vivado 12-3761] /home/ridgerun/customers/xilinx/rdf0428-20173/rdf0428-zcu106-vcu-trd-2017-3/pl/project/zcu106_vcu_trd.srcs/sources_1/bd/zcu106_vcu_trd/ip/zcu106_vcu_trd_v_mix_0_0/zcu106_vcu_trd_v_mix_0_0.xci: Synthesis target needs to be generated before calling compile_c.
Will check what could be causing this issue to happen.
02-02-2018 08:50 AM
Try to generate the output product for the BD before synthesizing the design.
02-02-2018 09:24 AM
First, this is no longer be a problem in 2017.3 and later, as the Zynq UltraScale+ MPSoC EV parts are no longer in Early Access.
The issue described above with the 2017.2 compilation of the rdf0428-zcu106 for 2017.2 is due to a licensing issue with the parts. The 7EV parts used in the project were still in early access in 2017.2 and required a special license, and a TCL command to enable them. But due to the way that HLS builds its parts list the parts were not always being added at install time.
Because some of the IP in the project are HLS based IP, they were failing to synthesize and then giving an error that the module could not be found. (i.e. the messages in the original post by @carlos.aguero)
To resolve this problem, you must first follow the License install instructions from the Early Access documentation. Once that is complete, you can manually regenerate the parts list for HLS using the following commands from a terminal.
<installRoot>/Vivado/2017.2/bin/vivado -nolog -nojournal -mode batch -source <installRoot>/.xinstall/Vivado_2017.2/scripts/xlpartinfo.tcl -tclargs <installRoot>/Vivado/2017.2/data/parts/installed_devices.txt
02-02-2018 09:46 AM
Thank you for your quick answer and complete explanation, I moved to 2017.3 and as you mentioned the original problem is not happening anymore because MPSoC EV parts are no longer in Early Access.
Now I got rdf0428 for 2017.3 but the problem reported is:
[Vivado 12-3761] [...]/ip/zcu106_vcu_trd_v_mix_0_0/zcu106_vcu_trd_v_mix_0_0.xci: Synthesis target needs to be generated before calling compile_c.
Seems that this is a possible solution: https://www.xilinx.com/support/answers/70182.html but seems to be not working on my case, not sure on how this patch works... I added the zip content at /opt/Xilinx/Vivado/2017.3/patches/AR70182_vivado_2017_3_preliminary_rev1/ and others but seems to be not working, probably need to check more at https://www.xilinx.com/support/answers/70182.html or check if I can get a full license for the vmix.
Regards and thanks for your time.
02-20-2018 08:21 AM
I have tried on windows and I am able to work with HW evaluation license in 2017.3 with the patch from AR#70182. Make sure you are using the MYVIVADO environment variable.