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Visitor nznkn
Visitor
710 Views
Registered: ‎06-04-2018

Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hello.

 

Vivado fails during synthesis for the attached project (which contains possibly errneous HDL source).

 

Syhthesis log ends with:

INFO: [Synth 8-4471] merging register 'q_b_wire_reg[31:0]' into 'q_a_wire_reg[31:0]' [C:/Users/yamada/Desktop/project_1/project_1.srcs/sources_1/new/main.v:13188]
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'C:/Users/yamada/Desktop/project_1/project_1.runs/synth_1/hs_err_pid11140.log' for details

 

hs_err_pid11140.log:

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

 

I'm using Xilinx Design Tools Vivado HL Design Edition 2018.2 (reproducible with 2018.1 too) on Windows 10.

 

Thank you.

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

Jump to solution

I can reproduce the issue with your code.

This is a tool issue. I will file a CR.

If you change the code like below to put q_a_wire and q_b_wire into different always blocks, the crash issue will not occur.

module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);

input clk;
input clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input wren_a;
input wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
if (clken)
begin
if (wren_a)
begin
if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
q_a_wire <= {32{1'bX}};
end
else
q_a_wire <= ram[address_a];
end

always @ (posedge clk)
if (clken)
begin
if (wren_b)
begin
if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
q_b_wire <= {32{1'bX}};
end
else
q_b_wire <= ram[address_b];
end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

 

But you'll receive another error:

Error:[Synth 8-2913] Unsupported Dual Port Block-RAM template for ram_reg.

For the correct Dual Port BRAM inference template, please refer to UG901.

-vivian

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5 Replies
Moderator
Moderator
690 Views
Registered: ‎07-21-2014

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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@nznkn

 

A quick question, what happens when you disable the register merging(-keep_equivalent_registers)?

 

Thanks

Anusheel

Thanks
Anusheel
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Highlighted
Visitor nznkn
Visitor
676 Views
Registered: ‎06-04-2018

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Nothing happened - synthesis still fails with the access violation.

 

Thanks

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Visitor nznkn
Visitor
652 Views
Registered: ‎06-04-2018

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

Jump to solution

I got smaller reproduction code:

module ram_dual_port
(
	clk,
	clken,
	address_a,
	address_b,
	wren_a,
	wren_b,
	data_a,
	data_b,
	byteena_a,
	byteena_b,
	q_a,
	q_b
);

input  clk;
input  clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input  wren_a;
input  wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
    if (clken)
    begin
        if (wren_a)
        begin
            if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
            q_a_wire <= {32{1'bX}};
        end
        else
            q_a_wire <= ram[address_a];
        if (wren_b)
        begin
            if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
            q_b_wire <= {32{1'bX}};
        end
        else
            q_b_wire <= ram[address_b];
    end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

module top(clk);
input clk;

reg  x_address_a;
reg  x_write_enable_a;
wire [31:0] x_in_a;
wire [31:0] x_out_a;
wire  x_address_b;
wire  x_write_enable_b;
wire [31:0] x_in_b;
wire [31:0] x_out_b;

ram_dual_port x (
	.clk( clk ),
	.clken( 1'b1 ),
	.address_a( x_address_a ),
	.address_b( x_address_b ),
	.wren_a( x_write_enable_a ),
	.wren_b( x_write_enable_b ),
	.data_a( x_in_a ),
	.data_b( x_in_b ),
	.byteena_a( 1'b1 ),
	.byteena_b( 1'b1 ),
	.q_a( x_out_a ),
	.q_b( x_out_b)
);

endmodule
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Explorer
Explorer
635 Views
Registered: ‎04-22-2015

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Silly question - how long has your computer been running?

If it's been more than 3 or 4 days since I rebooted my computer (Windows 7) I get nearly identical error as you.  Rebooting fixes it for a few more days.

ken

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Xilinx Employee
Xilinx Employee
626 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

Jump to solution

I can reproduce the issue with your code.

This is a tool issue. I will file a CR.

If you change the code like below to put q_a_wire and q_b_wire into different always blocks, the crash issue will not occur.

module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);

input clk;
input clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input wren_a;
input wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
if (clken)
begin
if (wren_a)
begin
if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
q_a_wire <= {32{1'bX}};
end
else
q_a_wire <= ram[address_a];
end

always @ (posedge clk)
if (clken)
begin
if (wren_b)
begin
if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
q_b_wire <= {32{1'bX}};
end
else
q_b_wire <= ram[address_b];
end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

 

But you'll receive another error:

Error:[Synth 8-2913] Unsupported Dual Port Block-RAM template for ram_reg.

For the correct Dual Port BRAM inference template, please refer to UG901.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------