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Visitor
Visitor
1,484 Views
Registered: ‎06-04-2018

Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hello.

 

Vivado fails during synthesis for the attached project (which contains possibly errneous HDL source).

 

Syhthesis log ends with:

INFO: [Synth 8-4471] merging register 'q_b_wire_reg[31:0]' into 'q_a_wire_reg[31:0]' [C:/Users/yamada/Desktop/project_1/project_1.srcs/sources_1/new/main.v:13188]
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'C:/Users/yamada/Desktop/project_1/project_1.runs/synth_1/hs_err_pid11140.log' for details

 

hs_err_pid11140.log:

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

 

I'm using Xilinx Design Tools Vivado HL Design Edition 2018.2 (reproducible with 2018.1 too) on Windows 10.

 

Thank you.

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Xilinx Employee
Xilinx Employee
1,399 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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I can reproduce the issue with your code.

This is a tool issue. I will file a CR.

If you change the code like below to put q_a_wire and q_b_wire into different always blocks, the crash issue will not occur.

module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);

input clk;
input clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input wren_a;
input wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
if (clken)
begin
if (wren_a)
begin
if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
q_a_wire <= {32{1'bX}};
end
else
q_a_wire <= ram[address_a];
end

always @ (posedge clk)
if (clken)
begin
if (wren_b)
begin
if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
q_b_wire <= {32{1'bX}};
end
else
q_b_wire <= ram[address_b];
end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

 

But you'll receive another error:

Error:[Synth 8-2913] Unsupported Dual Port Block-RAM template for ram_reg.

For the correct Dual Port BRAM inference template, please refer to UG901.

-vivian

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14 Replies
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Moderator
Moderator
1,464 Views
Registered: ‎07-21-2014

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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@nznkn

 

A quick question, what happens when you disable the register merging(-keep_equivalent_registers)?

 

Thanks

Anusheel

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Visitor
Visitor
1,450 Views
Registered: ‎06-04-2018

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Nothing happened - synthesis still fails with the access violation.

 

Thanks

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Visitor
Visitor
1,426 Views
Registered: ‎06-04-2018

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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I got smaller reproduction code:

module ram_dual_port
(
	clk,
	clken,
	address_a,
	address_b,
	wren_a,
	wren_b,
	data_a,
	data_b,
	byteena_a,
	byteena_b,
	q_a,
	q_b
);

input  clk;
input  clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input  wren_a;
input  wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
    if (clken)
    begin
        if (wren_a)
        begin
            if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
            q_a_wire <= {32{1'bX}};
        end
        else
            q_a_wire <= ram[address_a];
        if (wren_b)
        begin
            if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
            q_b_wire <= {32{1'bX}};
        end
        else
            q_b_wire <= ram[address_b];
    end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

module top(clk);
input clk;

reg  x_address_a;
reg  x_write_enable_a;
wire [31:0] x_in_a;
wire [31:0] x_out_a;
wire  x_address_b;
wire  x_write_enable_b;
wire [31:0] x_in_b;
wire [31:0] x_out_b;

ram_dual_port x (
	.clk( clk ),
	.clken( 1'b1 ),
	.address_a( x_address_a ),
	.address_b( x_address_b ),
	.wren_a( x_write_enable_a ),
	.wren_b( x_write_enable_b ),
	.data_a( x_in_a ),
	.data_b( x_in_b ),
	.byteena_a( 1'b1 ),
	.byteena_b( 1'b1 ),
	.q_a( x_out_a ),
	.q_b( x_out_b)
);

endmodule
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Explorer
Explorer
1,409 Views
Registered: ‎04-22-2015

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Silly question - how long has your computer been running?

If it's been more than 3 or 4 days since I rebooted my computer (Windows 7) I get nearly identical error as you.  Rebooting fixes it for a few more days.

ken

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Xilinx Employee
Xilinx Employee
1,400 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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I can reproduce the issue with your code.

This is a tool issue. I will file a CR.

If you change the code like below to put q_a_wire and q_b_wire into different always blocks, the crash issue will not occur.

module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);

input clk;
input clken;
input [(1-1):0] address_a;
input [(1-1):0] address_b;
output wire [31:0] q_a;
output wire [31:0] q_b;
reg [31:0] q_a_wire;
reg [31:0] q_b_wire;
input wren_a;
input wren_b;
input [31:0] data_a;
input [31:0] data_b;
input [1-1:0] byteena_a;
input [1-1:0] byteena_b;

reg [32-1:0] ram[1-1:0];

always @ (posedge clk)
if (clken)
begin
if (wren_a)
begin
if (byteena_a[0]) ram[address_a][0 +: 32] <= data_a[0 +: 32];
q_a_wire <= {32{1'bX}};
end
else
q_a_wire <= ram[address_a];
end

always @ (posedge clk)
if (clken)
begin
if (wren_b)
begin
if (byteena_b[0]) ram[address_b][0 +: 32] <= data_b[0 +: 32];
q_b_wire <= {32{1'bX}};
end
else
q_b_wire <= ram[address_b];
end

assign q_a = (clken) ? q_a_wire : 0;
assign q_b = (clken) ? q_b_wire : 0;

endmodule

 

But you'll receive another error:

Error:[Synth 8-2913] Unsupported Dual Port Block-RAM template for ram_reg.

For the correct Dual Port BRAM inference template, please refer to UG901.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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Highlighted
Visitor
Visitor
731 Views
Registered: ‎04-28-2017

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hello,

Can I get an update on the status of a fix for the EXCEPTION_ACCESS_VIOLATION in Vivado?  My customer is not able to synthesize due to this error.  I see that since Vivado 2017 the solution has been that a fix will be in a future Vivado release.  But I am using Vivado 2019.1 to replicate his error with our IP.  Synthesis simply fails with no error other than "EXCEPTION_ACCESS_VIOLATION."

I am trying the black box attribute to isolate the module triggering this error.  Other than waiting for a fix in a future Vivado release, what is the recommended work-around?

Thank you,

Erin

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Xilinx Employee
Xilinx Employee
707 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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@erinlsalter The original issue in this thread has been fixed in 2019.1.

EXCEPTION_ACCESS_VIOLATION is kind of error like crash where the tool is not able to report where the exact problem is.

Not all issues with this error have the same root cause.

If you encounter this error in 2019.1, yours is another different issue.

If you can find out the module that triggers the error, please share it and we can try to fix the problem in the tool, and find a workaround for you as well,

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Highlighted
Visitor
Visitor
690 Views
Registered: ‎04-28-2017

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Thank you, Vivian.

I am using Vivado 2019.1.2, and have tried multiple devices for the project with the same result.  Using the black_box attribute, I have isolated the triggering code to the following:

module logic_reset_circuit (
scan_mode_in,
scan_rstn_in,
clk,
ByteClkHS,
Enable,
ForceTxStopmode,
ForceRxmode,
d_ForceTxStopmode,
d_ForceRxmode,
reset_n,
reset_n_byte,
enable_sync_scan,
enable_sync
);

input scan_mode_in;
input scan_rstn_in;
input clk;
input ByteClkHS;
input Enable;
input ForceTxStopmode;
input ForceRxmode;
output d_ForceTxStopmode;
output d_ForceRxmode;
output reset_n;
output reset_n_byte;
output enable_sync_scan;
output enable_sync;

reg d_ForceTxStopmode; 
reg d_ForceRxmode; 
wire Enable_SYNC;
reg Enable_SYNC1;
reg reset_n_byte1;
wire reset_n_byte;

wire Enable_int;
reg Enable_SYNC_int;
wire reset_n_int;
reg reset_n_byte_int;

 

assign Enable_int = scan_mode_in ? scan_rstn_in : Enable;

always @ (posedge clk or negedge Enable_int)
begin
if (~Enable_int)
begin
Enable_SYNC1 <= 1'b0;
Enable_SYNC_int <= 1'b0;
end
else
begin
Enable_SYNC1 <= 1'b1;
Enable_SYNC_int <= Enable_SYNC1;
end
end

assign reset_n_int = Enable_SYNC_int & ~ForceRxmode & ~ForceTxStopmode;

assign reset_n = scan_mode_in ? scan_rstn_in : reset_n_int;

always @ (posedge ByteClkHS or negedge reset_n)
begin
if (~reset_n)
begin
reset_n_byte1 <= 1'b0;
reset_n_byte_int <= 1'b0;
end
else
begin
reset_n_byte1 <= 1'b1;
reset_n_byte_int <= reset_n_byte1;
end
end

assign reset_n_byte = scan_mode_in ? scan_rstn_in : reset_n_byte_int;

assign Enable_SYNC = scan_mode_in ? scan_rstn_in : Enable_SYNC_int;

always @ (posedge clk or negedge Enable_SYNC)
begin
if (~Enable_SYNC)
d_ForceTxStopmode <= 1'b0;
else if (ForceTxStopmode) // set when detected
d_ForceTxStopmode <= 1'b1;
else if (reset_n_int) // reset after reset_n is deasserted
d_ForceTxStopmode <= 1'b0;
end

always @ (posedge clk or negedge Enable_SYNC)
begin
if (~Enable_SYNC)
d_ForceRxmode <= 1'b0;
else if (ForceRxmode) // set when detected
d_ForceRxmode <= 1'b1;
else if (reset_n_int) // reset after reset_n is deasserted
d_ForceRxmode <= 1'b0;
end

assign enable_sync = Enable_SYNC_int; // *** Before scan mux
assign enable_sync_scan = Enable_SYNC; // *** After scan mux

endmodule

 

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Xilinx Employee
Xilinx Employee
668 Views
Registered: ‎02-16-2014

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hi @erinlsalter 

Can you provide me with vivado log file ? Are you running synth_design with any switches?

I tried code shared by you and the design gets synthesized without any issues at my end in 2019.1.2.

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Visitor
Visitor
658 Views
Registered: ‎04-28-2017

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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I was able to reach successful synthesis yesterday and unfortunately don't have this logfile any more. 

This same module copied in this thread was used in a larger design and synthesized successfully there.  What finally worked was adding the larger design to this project so there was a different top-level module.  Once synthesized, I removed the new top-level module and synthesized the original IP - successfully this time.

My theory at this point is that the I/O of the original IP exceeded the I/O of the xc7k325.  And this was due to ports that would normally connect to other logic within the device, but in the absence of a larger design were left as top-level ports.  After getting a successful synthesis run, I ran implementation and these were the first warning messages.  Does it seem reasonable that synthesis might crash with the EXCEPTION_ACCESS_VIOLATION if too many I/O ports for the device are detected?

I am waiting to hear that my customer can synthesize once importing the IP into his larger design.  I'm not sure the failure is completely explained, but hopefully resolved...

Thank you,

Erin

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Visitor
Visitor
636 Views
Registered: ‎04-28-2017

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hello again,

I created a top-level wrapper for my customer's IP and am still getting a synthesis crash with the same EXCEPTION_ACCESS_VIOLATION.  I do have log files from the synthesis run, but is it possible to send these directly to Xilinx for review?  Some sensitive information should not be publicly shared.

Thank you,

Erin

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Xilinx Employee
Xilinx Employee
627 Views
Registered: ‎02-16-2014

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hi @erinlsalter 

 

I have sent you private message. Please check.

I will send you link to upload files.

 

Thanks,

Manusha

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Xilinx Employee
Xilinx Employee
615 Views
Registered: ‎05-14-2008

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Does this customer's IP have anything to do with the code snippet you provided above?

Can you pin point the portion of the design that can be used to reproduce the error when synthesizing this portion standalone?

The code snipped you provided above actually cannot reproduce the error.

Can you provide your email box so that I can send you an EZMOVE link for you to upload your log file or any source files safely?

-vivian

 

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Visitor
Visitor
603 Views
Registered: ‎04-28-2017

Re: Synthesis failed with EXCEPTION_ACCESS_VIOLATION

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Hi Vivian,

I am suspicious that the portion of code I wrapped in the black box attribute (and pasted above) is the actual problem.  This same portion of code was used in another design successfully.  I suspect it may be the upper-level connections that provide input to this block.

I just sent Manusha my email in response to the private message.  Please let me know if you do not have access.

Thank you,

Erin

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