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Visitor
Visitor
11,832 Views
Registered: ‎01-20-2016

Synthesis failed without reporting any error

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Here is the log when I hit run synthesis in Vivado 2015.4

 

*** Running vivado
with args -log aes_encrypt.vds -m64 -mode batch -messageDb vivado.pb -notrace -source aes_encrypt.tcl


****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source aes_encrypt.tcl -notrace
Command: synth_design -top aes_encrypt -part xc7k70tfbv676-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k70t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k70t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 9855
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1047.977 ; gain = 193.707 ; free physical = 88 ; free virtual = 28405
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'aes_encrypt' [/home/agohil/proj/block2tests/src/dsn/aes_encrypt.sv:3]
Parameter Nk bound to: 4 - type: integer
Parameter Nr bound to: 10 - type: integer
INFO: [Synth 8-638] synthesizing module 'aes_key_expand' [/home/agohil/proj/block2tests/src/dsn/aes_key_expand.sv:3]
Parameter Nk bound to: 4 - type: integer
Parameter Nr bound to: 10 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aes_key_expand' (1#1) [/home/agohil/proj/block2tests/src/dsn/aes_key_expand.sv:3]
INFO: [Synth 8-638] synthesizing module 'aes_cipher' [/home/agohil/proj/block2tests/src/dsn/aes_cipher.sv:4]
Parameter Nk bound to: 4 - type: integer
Parameter Nr bound to: 10 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aes_cipher' (2#1) [/home/agohil/proj/block2tests/src/dsn/aes_cipher.sv:4]
INFO: [Synth 8-256] done synthesizing module 'aes_encrypt' (3#1) [/home/agohil/proj/block2tests/src/dsn/aes_encrypt.sv:3]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1192.500 ; gain = 338.230 ; free physical = 104 ; free virtual = 28257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1192.500 ; gain = 338.230 ; free physical = 104 ; free virtual = 28257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k70tfbv676-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1200.500 ; gain = 346.230 ; free physical = 104 ; free virtual = 28257
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k70tfbv676-1
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1323.254 ; gain = 468.984 ; free physical = 111 ; free virtual = 28148
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
3 Input 32 Bit XORs := 1
2 Input 32 Bit XORs := 74
4 Input 32 Bit XORs := 1
5 Input 32 Bit XORs := 1
6 Input 32 Bit XORs := 1
7 Input 32 Bit XORs := 1
8 Input 32 Bit XORs := 1
9 Input 32 Bit XORs := 1
10 Input 32 Bit XORs := 1
11 Input 32 Bit XORs := 1
12 Input 32 Bit XORs := 1
2 Input 8 Bit XORs := 216
4 Input 8 Bit XORs := 144
+---Registers :
128 Bit Registers := 11
8 Bit Registers := 150
1 Bit Registers := 11
+---ROMs :
ROMs := 150
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module aes_key_expand
Detailed RTL Component Info :
+---XORs :
3 Input 32 Bit XORs := 1
2 Input 32 Bit XORs := 30
4 Input 32 Bit XORs := 1
5 Input 32 Bit XORs := 1
6 Input 32 Bit XORs := 1
7 Input 32 Bit XORs := 1
8 Input 32 Bit XORs := 1
9 Input 32 Bit XORs := 1
10 Input 32 Bit XORs := 1
11 Input 32 Bit XORs := 1
12 Input 32 Bit XORs := 1
Module aes_cipher
Detailed RTL Component Info :
+---XORs :
2 Input 32 Bit XORs := 44
2 Input 8 Bit XORs := 216
4 Input 8 Bit XORs := 144
+---Registers :
128 Bit Registers := 11
8 Bit Registers := 150
1 Bit Registers := 11
+---ROMs :
ROMs := 150
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary

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Xilinx Employee
Xilinx Employee
22,093 Views
Registered: ‎04-16-2012

Re: Synthesis failed without reporting any error

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Hi @qubits1

 

I suspect the issue here is unsupported OS.

Can you check run synthesis on the same project on a supported OS. Check the following user guide for supported OS: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug973-vivado-release-notes-install-license.pdf

 

Thanks,

Vinay

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Visitor
Visitor
11,828 Views
Registered: ‎01-20-2016

Re: Synthesis failed without reporting any error

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There is one more line in the log.

---------------------------------------------------------------------------------
Parent process (pid 9847) has died. This helper process will now exit

 

 

I'm running this in Ubuntu 15.10

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Xilinx Employee
Xilinx Employee
22,094 Views
Registered: ‎04-16-2012

Re: Synthesis failed without reporting any error

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Hi @qubits1

 

I suspect the issue here is unsupported OS.

Can you check run synthesis on the same project on a supported OS. Check the following user guide for supported OS: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug973-vivado-release-notes-install-license.pdf

 

Thanks,

Vinay

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Moderator
Moderator
11,556 Views
Registered: ‎07-21-2014

Re: Synthesis failed without reporting any error

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@qubits1

 

>>I'm running this in Ubuntu 15.10

Ubuntu 15.10 is not supported with Vivado. Try to use supported OS and see if you are able to pass the synthesis phase.

 

Thanks,
Anusheel
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Contributor
Contributor
11,180 Views
Registered: ‎02-11-2014

Re: Synthesis failed without reporting any error

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I just ran into this error as well on Ubuntu 15.10. Is Ubuntu 16.04 support coming? It's an LTS release so many will be upgrading.

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Highlighted
10,817 Views
Registered: ‎03-09-2016

Re: Synthesis failed without reporting any error

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I am running on a Windows machine (supported OS) and I get the same type of failure.

 

Here is the end of my log

 

---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 120 (col length:60)
BRAMs: 150 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes.
Start Parallel Synthesis Optimization  : Time (s): cpu = 00:01:37 ; elapsed = 00:01:48 . Memory (MB): peak = 862.031 ; gain = 690.270

 

 

I will continue searching for a solution

 

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