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Contributor
Contributor
2,048 Views
Registered: ‎01-04-2017

Synthesis fails with no errors or warnings

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Hello Everybody here! Sorry for creating post which it has solved already, but I couldn't find any solution from the threads posted before.

I'm trying write simple demux1to32 code  inserted below 

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demux_1to32 is
 port(

 D : in STD_LOGIC;
 S: in STD_LOGIC_VECTOR (4 downto 0);
 Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26,Q27,Q28,Q29,Q30,Q31: out STD_LOGIC
 );
end demux_1to32;

architecture bhv of demux_1to32 is
begin
process (D,S) 
begin
 if (S="00000") then
 Q0 <= D;
 elsif (S="00001") then
 Q1 <= D;
 elsif (S="00010") then
 Q2 <= D;
 elsif (S="00011") then
 Q3 <= D;
 elsif (S="00100") then
 Q4 <= D;
 elsif (S="00101") then
 Q5 <= D;
 elsif (S="00110") then
 Q6 <= D;
 elsif (S="00111") then
 Q7 <= D;
 elsif (S="01000") then
 Q8 <= D;
 elsif (S="01001") then
 Q9 <= D;
 elsif (S="01010") then
 Q10 <= D;
 elsif (S="01011") then
 Q11 <= D;
 elsif (S="01100") then
 Q12 <= D;
 elsif (S="01101") then
 Q13 <= D;
 elsif (S="01110") then
 Q14 <= D;
 elsif (S="01111") then
 Q15 <= D;
 elsif (S="10000") then
 Q16 <= D;
 elsif (S="10001") then
 Q17 <= D;
 elsif (S="10010") then
 Q18 <= D;
 elsif (S="10011") then
 Q19 <= D;
 elsif (S="10100") then
 Q20 <= D;
 elsif (S="10101") then
 Q21 <= D;
 elsif (S="10110") then
 Q22 <= D;
 elsif (S="10111") then
 Q23 <= D;
 elsif (S="11000") then
 Q24 <= D;
 elsif (S="11001") then
 Q25 <= D;
 elsif (S="11010") then
 Q26 <= D;
 elsif (S="11011") then
 Q27 <= D;
 elsif (S="11100") then
 Q28 <= D;
 elsif (S="11101") then
 Q29 <= D;
 elsif (S="11110") then
 Q30 <= D;
 else
 Q31 <= D;
 end if;

end process;
end bhv;

Simulation is working fine, but synthesis fails with no errors or warnings. Restarting project or restarting computer didn't help. I've noticed when I change last sequential statement to 

elsif (S="11111") then
Q31 <= D;

 synthesis is working also, but I got following warnings:

  • [Synth 8-327] inferring latch for variable 'Q0_reg' ["C:/xilinx/demux_f.pro/demux_f.pro.srcs/sources_1/new/design.source":18]
  • [Synth 8-327] inferring latch for variable 'Q1_reg' ["C:/xilinx/demux_f.pro/demux_f.pro.srcs/sources_1/new/design.source":20]

 Please, tell me : 'Can I ignore these warnings or how to get rid of them?'

Thanks in advance. 

 

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1 Solution

Accepted Solutions
Scholar embedded
Scholar
3,146 Views
Registered: ‎06-09-2011

Re: Synthesis fails with no errors or warnings

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@marzhan_123,

First, you are better to use std_logic_vector as the output and then use something else for your coding to make it more readable.

It seems something incomplete with your code!. You are better specify every output state in every condition. 

This piece in entity

Q : out std_logic_vector(31 downto 0);

 

if S = "0000" then
 Q(0) <= D;
Q(31 downto1) <= (others => '0');
elsif 
..

Hope this helps,

Hossein

 

View solution in original post

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5 Replies
Scholar embedded
Scholar
3,147 Views
Registered: ‎06-09-2011

Re: Synthesis fails with no errors or warnings

Jump to solution

@marzhan_123,

First, you are better to use std_logic_vector as the output and then use something else for your coding to make it more readable.

It seems something incomplete with your code!. You are better specify every output state in every condition. 

This piece in entity

Q : out std_logic_vector(31 downto 0);

 

if S = "0000" then
 Q(0) <= D;
Q(31 downto1) <= (others => '0');
elsif 
..

Hope this helps,

Hossein

 

View solution in original post

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Moderator
Moderator
2,034 Views
Registered: ‎11-09-2015

Re: Synthesis fails with no errors or warnings

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Hi @marzhan_123,

 

It depends on how your demux should work.

 

This warning means that the output will keep its previous value when it is not selected.

 

If you want to remove the warning you might want to change your code with something like:

if (S="00000") then
 Q0 <= D;
else
Q0 <= (others => 0); -- if you want to reset the output if not selected
-- Q0 <= (others => 0); -- if you want to keep the output value if not selected
end if;i

if (S="00001") then Q1 <= D;
else
...

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
2,033 Views
Registered: ‎09-15-2016

Re: Synthesis fails with no errors or warnings

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Hi @marzhan_123,

 

I am able to reproduce the issue where "the tool is not throwing any errors/warnings" for the RTL as it fails in synthesis in Vivado 2017.2. This should not happen, as the tool is expected to give some message for the error it is detecting.

 

I tired the above in ISE 14.7 where XST passes the above code and synthesizes a 1 to 32 demux but with a proper message that latch is inferred for the above logic.

 

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Moderator
Moderator
1,898 Views
Registered: ‎09-15-2016

Re: Synthesis fails with no errors or warnings

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I have filed a CR-985890 for the issue "Synthesis fails without error message; but with Segmentation fault (core dumped) "$RDI_PROG" "$@" Parent process (pid 43828) has died." for the following reason:

 

- The tool throws synthesis failure with the initial code (untouched) without a message for default run. 

I guess optimization must not matter here, but tool is expected to indicate a message to user as to what the issue is> memory/crash/code not optimized/incomplete if-else etc.?

 

Thanks & Regards,

Prathik

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Highlighted
Moderator
Moderator
1,499 Views
Registered: ‎09-15-2016

Re: Synthesis fails with no errors or warnings

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Hi,

 

The above CR-985890 issue is fixed in Vivado 2018.1 (internal).

 

Regards,
Prathik
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