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fernands
Visitor
Visitor
269 Views
Registered: ‎07-16-2019

Synthesis fails without any message

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Hi everyone,

I can't seem to synthesize my design, Vivado (v 2017.4) just says "Synthesis failed" without any message. I attach the hs_err log file in this message. Any help is more  than welcome, thanks in advance.

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aher
Xilinx Employee
Xilinx Employee
222 Views
Registered: ‎07-21-2014

Hi,

The issue looks to be around instantiation under generate loop. 

Is it possible to synthesize the design using latest vivado build or share rtl design?

 

-Shreyas

 

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aher
Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎07-21-2014

Hi,

The issue looks to be around instantiation under generate loop. 

Is it possible to synthesize the design using latest vivado build or share rtl design?

 

-Shreyas

 

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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fernands
Visitor
Visitor
193 Views
Registered: ‎07-16-2019

Thanks a lot, I review my code and found the error. How could I have seen this from the report?

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