07-27-2021 09:12 AM
Dear Xilinx community members,
We are looking for Block RAM ECC synthesis inference templates (to have complete portability of the code to multiple architectures) to be used in an UltraScale+ device.
In ug573, Chapter 1, section "Built-in Error Correction", the following is indicated:
"Block RAM ECC VHDL and Verilog Templates
VHDL and Verilog templates are available in the Vivado Design Suite."
However in Vivado Design Suite Language Templates I can only find synthesis inference templates (Synthesis constructs -> Example Modules or Coding Examples) without ECC (see attached image).
Do the Block RAM ECC templates, mentioned in ug573, only apply for primitive instantiations and XPMs but not for synthesis inference? Is there a way to infer Block RAM with ECC?
07-29-2021 02:12 AM
Thanks for your reply.
Yes, I had looked at UG901 and saw no reference to synthesis inference templates for RAMs with ECC.
By now we assume there is none, but if any other Xilinx community member knows about it and could point us to the template, I would really appreciate his/her answer.
07-29-2021 07:36 AM
In UG573, try to click on this:
It could be a documentation error, and this feedback (last time I tried it) goes to the document author (or person now responsible for the document).
Or contact your FAE.