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835 Views
Registered: ‎02-17-2018

Synthesis is True, but...

 i have an issue on my vhdl program. I want to  implement bluetooth car module fpga based dual dc motor control. I'm using spartan3 starter kit. My code give me no error and warnings. so, i synthesized and implemented the code. And generate the programing file and i did necesaary connections on it (impact). then, when i push the backward button  on android apps the first and second dc motor have 3.3 V. Then push the forward button, the dual dc motor have 1.1V each of it. at the same time right and left button 1.1V too. why I can not see 3.3V each of it. Do you have any ideas on how to fix this issue? 

 

Here is my code. Please give me a specific answer. Where is my mistake? I have been scrambling for almost 2 weeks and have not found a solution.

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5 Replies
Voyager
Voyager
832 Views
Registered: ‎06-20-2017

Re: Synthesis is True, but...

Could you also upload your testbench that provides the expected stimulus and tests for the expected output?

Adaptable Processing coming to an IP address near you.
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810 Views
Registered: ‎02-17-2018

Re: Synthesis is True, but...

Here is my test bench for sub_module...

 

I have no idea for receiving bluetooth data test bench stimulus process. That's why i wrote just sub_module test bench. 


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Voyager
Voyager
798 Views
Registered: ‎06-20-2017

Re: Synthesis is True, but...

Does your waveform match what you want?

Adaptable Processing coming to an IP address near you.
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756 Views
Registered: ‎02-17-2018

Re: Synthesis is True, but...

Yeah, as I want the waveform. But  just sub_module . may be an error in  the top module (i missed it), even so, Isn't it very strange not to give a synthesis error?  because the circuit outputs aren't what I want. I want to all of outputs 3.3V ( not just one). i don't know , could i explain this issue as good as enough. 

 

Thank u for attention anyway.

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Voyager
Voyager
732 Views
Registered: ‎06-20-2017

Re: Synthesis is True, but...


@los_galacticos wrote:

Yeah, as I want the waveform. But  just sub_module . may be an error in  the top module (i missed it), even so, Isn't it very strange not to give a synthesis error?  because the circuit outputs aren't what I want. I want to all of outputs 3.3V ( not just one). i don't know , could i explain this issue as good as enough. 

 

Thank u for attention anyway.


Take a look at UG937.  You should be able to see into your design below the top level.

Adaptable Processing coming to an IP address near you.
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