UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor faizan.sayed
Visitor
163 Views
Registered: ‎04-05-2018

Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

Hi Xilinx Team,

I would like to report a synthesis issue which took us days to figure out in complete design.

Figure below shows the code snippet where it failed to synthesize correctly(what we expected) in xilinx vivado 2018.x version.
Note: Code is Legacy code proven on ASIC and Xilinx Virtex 6 FPGA with synopsis synplify pro synthesis.
original.png

 

Finally we had to update the code for compatibility with Vivado with following changes:

fixed RTL.PNG

 Regards,

Faizan Sayed

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
153 Views
Registered: ‎02-16-2014

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

Hi @faizan.sayed

Is it possible for you to share the design to debug this issue further?

 

Thanks,

Manusha

0 Kudos
Visitor faizan.sayed
Visitor
143 Views
Registered: ‎04-05-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

Hi Manusha,

This particular Problem got solved as stated in the ticket image number 2.we had to change the RTL to make it compatible with Vivado and synplify pro.

we are facing now another issue of same kind,which we are not able to solve with above changes. still we are looking for solution .
i can share only code snippet, where we are having issue and design checkpoint file remotely.

Regards,
Faizan Sayed
0 Kudos
Scholar richardhead
Scholar
122 Views
Registered: ‎08-01-2012

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

Without a full code example showing the problem its difficult to understand really what the problem is.

Your code shows no declarations or packages used.

You do not state what "synthesised correctly" means. 

0 Kudos