01-07-2019 10:52 PM
Hi Xilinx Team,
I would like to report a synthesis issue which took us days to figure out in complete design.
Figure below shows the code snippet where it failed to synthesize correctly(what we expected) in xilinx vivado 2018.x version.
Note: Code is Legacy code proven on ASIC and Xilinx Virtex 6 FPGA with synopsis synplify pro synthesis.
Finally we had to update the code for compatibility with Vivado with following changes:
01-07-2019 11:02 PM
01-07-2019 11:13 PM
01-08-2019 01:25 AM - edited 01-08-2019 01:26 AM
Without a full code example showing the problem its difficult to understand really what the problem is.
Your code shows no declarations or packages used.
You do not state what "synthesised correctly" means.