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Visitor faizan.sayed
Visitor
869 Views
Registered: ‎04-05-2018

Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Hi Xilinx Team,

I would like to report a synthesis issue which took us days to figure out in complete design.

Figure below shows the code snippet where it failed to synthesize correctly(what we expected) in xilinx vivado 2018.x version.
Note: Code is Legacy code proven on ASIC and Xilinx Virtex 6 FPGA with synopsis synplify pro synthesis.
original.png

 

Finally we had to update the code for compatibility with Vivado with following changes:

fixed RTL.PNG

 Regards,

Faizan Sayed

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1 Solution

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Visitor faizan.sayed
Visitor
661 Views
Registered: ‎04-05-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Filed Service Request for this issue. SR#10456912

Product Application Engineers fom Xilinx looked into this issue and reported this as BUG. Xilinx PAE suggested that this issue will be solved via an update for curent versions of Vivado and next version vivado 2019.1

8 Replies
Xilinx Employee
Xilinx Employee
859 Views
Registered: ‎02-16-2014

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Hi @faizan.sayed

Is it possible for you to share the design to debug this issue further?

 

Thanks,

Manusha

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Visitor faizan.sayed
Visitor
849 Views
Registered: ‎04-05-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Hi Manusha,

This particular Problem got solved as stated in the ticket image number 2.we had to change the RTL to make it compatible with Vivado and synplify pro.

we are facing now another issue of same kind,which we are not able to solve with above changes. still we are looking for solution .
i can share only code snippet, where we are having issue and design checkpoint file remotely.

Regards,
Faizan Sayed
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Scholar richardhead
Scholar
828 Views
Registered: ‎08-01-2012

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Without a full code example showing the problem its difficult to understand really what the problem is.

Your code shows no declarations or packages used.

You do not state what "synthesised correctly" means. 

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Visitor faizan.sayed
Visitor
662 Views
Registered: ‎04-05-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

Jump to solution

Filed Service Request for this issue. SR#10456912

Product Application Engineers fom Xilinx looked into this issue and reported this as BUG. Xilinx PAE suggested that this issue will be solved via an update for curent versions of Vivado and next version vivado 2019.1

Visitor nvt03266
Visitor
222 Views
Registered: ‎06-07-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Dear Sir,

I am Novatek CAD/PoChun. We now using 2019.1 vivado and get signed comparsion problem as this issue.

Is there any solution by changing tool command instead of RTL code?

Best Regards,
PoChun.

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Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎02-16-2014

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Hi @nvt03266 

Is it possible for you to share testcase so that I can check at my end if there is any tool command to workaround this issue.

If you can provide testcase that will help in fixing this issue in next vivado release.

if you can share files, please let me know I will share link where you can upload files to xilinx.

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Visitor nvt03266
Visitor
170 Views
Registered: ‎06-07-2018

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Dear Sir,

Thanks.
I will prepare the testcase download.
you can provide the uplaod IP. I should apply it to IT for opening firewall.

Best Regards,
PoChun.

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Xilinx Employee
Xilinx Employee
127 Views
Registered: ‎02-16-2014

Re: Synthesis issue : Signed Comparison synthesis issue (Ultrascale + Vivado 2018.x + Poven code on ASIC and earlier FPGA)

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Hi PoChun,

 

I tried RTL share by you in 2019.1 and the netlist generated is proven equivalent.

What is the issue that you are seeing? Are you using any simulation setup to validate this design?

Are you running vivado synthesis with default settings or are you using any switches?

 

Thanks,

Manusha

 

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