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Highlighted
1,077 Views
Registered: ‎06-18-2014

Synthesis issue in Vivado

Hello,

I've written a module (a cdc-fifo) in VHDL with ISE for Spartan-3e. It worked without problems.

Then, I used the same code in Vivado 2016.4/2018.3/2019.1. The synthesis runs w/o problems. However, the module does not work in the FPGA (Artix-7): The fifo did not store the write data. I found, that rewriting some lines were a work around of the issue. The synthesis of the original code "forgets" to increment the write-adress and let it on the initial value (=0).

For improving the quality of vivado synthesis I would provide the whole project to Xilinx.

Best regards,

Jens

 

Original code piece:

if (wr_en_i = '1') then
  if (v.full = '0') then
    v.mem_wr_en := '1';
    v.wr_adr := r_wr.wr_adr + 1;
  else
    v.overflow := '1';
  end if;
end if;

Work around:

if (wr_en_i = '1') then
  if (v.full = '0') then
    v.mem_wr_en := '1';
  else
    v.overflow := '1';
  end if;
end if;

if (wr_en_i = '1') and (v.full = '0') then
  v.wr_adr := r_wr.wr_adr + 1;
end if;

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23 Replies
Highlighted
Teacher
Teacher
1,050 Views
Registered: ‎07-09-2009

have you simulated ?
vivado is very different to ISE in terms of how it handles clocks,
What timing constraints have you used ? They are the Key.

Out of interest, why have you not just used the free fifo IP built into Vivado ?

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Highlighted
Moderator
Moderator
1,015 Views
Registered: ‎03-16-2017

@jens.schoenherr 

Kindly check behavioral simulation and post-synthesis functional simulation to see if you are getting correct functionality as per your expectations or not. If you are getting the wrong functionality then provide that specific signal name/cell name to evaluate it further.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Highlighted
993 Views
Registered: ‎06-18-2014

The wrong functionality can easily be seen in the synthesis netlist, generated by

1. open synthesized design

2. write_verilog -force abc.v

Both netlists differ a lot (2148 loc vs. 1420 loc) which should not be the case for nearly equivalent VHDL code.

Regards,

Jens

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Highlighted
Teacher
Teacher
988 Views
Registered: ‎07-09-2009

I think you are miss understanding how the tools work,

They impliment your algorithum / function, they do not impliment the code verbatum.

 

As far as the tools are concerned,  they have two points.

 

a) impliment the function / algorithum you specify

b) meet the timmings you specify

 

To meet (a) , different tools, versions of tools , can impliment the function in very different ways, The tools are getting smarter and much more efficient at making desingns, They push back and forward registers, add duplicatoin to meet the timming requirments  and optimise usage.

 

To prove to yourself that the two are the same, you need to run a test bench,

     Can you share that with us please

 

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Highlighted
983 Views
Registered: ‎06-18-2014

I used two functionally equivalent but syntactically different version of the same VHDL-module with the same synthesis tool (Vivado 2019.1). However, I got two different synthesis results. One is running on hardware and the other not.

Unfortunately, I have no testbench of the fifo module in question since I simulated it together with the module that instantiates the module in question.

Regards,

Jens

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Highlighted
Teacher
Teacher
979 Views
Registered: ‎07-09-2009

You need to

a) use a test bench to check functionality

b) check your timming constraints

 

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968 Views
Registered: ‎06-18-2014

Considering,
fifo_1.vhd --> synthesized to fifo_1_net.v
fifo_2.vhd --> synthesized to fifo_2_net.v
An equivalence checking tool (formal verification) should show that
fifo_1.vhd = fifo_2.vhd
fifo_1_net.v /= fifo_1.vhd !
fifo_2_net.v = fifo_2.vhd (= fifo_1.vhd)

Changing timing constraints should not have influence here. This would mean that changing a timing constraint transforms a constant register to a counter!

Regards,
Jens
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Highlighted
Teacher
Teacher
963 Views
Registered: ‎07-09-2009

Sorry

we have given you the test you need to do ( which you fail to do ) , and our expertise on what the diffierence is in ISE to vivado,

If you would like to do the simulation to porve the two are the same or different , and then add timming constraints to your desing and synthesis , then get back please.

 

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Highlighted
943 Views
Registered: ‎06-18-2014

I've now written a minimal tb to show the difference between the different versions. I've appended the waveforms.

fifo_1_rtl: simulation of the original fifo_1 in VHDL. One can see at 230ns that rd_empty_o becomes 0 because a data has been written some time before.

fifo_1_net: simulation of the synthesized functional model of fifo_1. One can see that rd_empty_o stays 1.

fifo_2_rtl: simulation of fifo_2 VHDL (changes to fifo_1 see in the first entry of this forum thread). Same behavior as fifo_1_rtl

fifo_2_net: simulation of the synthesized functional model of fifo_2. Same behavior as the RTL ("behavioral") simulations.

Regards,

Jens

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Highlighted
Explorer
Explorer
927 Views
Registered: ‎06-25-2014

I dont get your code, you are using varible assignments (i.e. := instead of <= ) You also don't show the process this code is running in, is it a clocked process? (I personaly would only ever use a variable on simple combinational elements and never on registers)

I think probably the reason you are seeing differences is due to your coding style being a bit on the edge of what the synthesis engine can interpret where ISE is ok.

This is only a guess though, but have seen this type of thing many times before.. 

Highlighted
890 Views
Registered: ‎06-18-2014

I use the Gaisler-style https://www.gaisler.com/doc/vhdl2proc.pdf

The variables are used inside the combinational process. However, every synthesis tool after milienium should translate this.

I would prefer to hand over the code (the whole Vivado-project) to Xilinx for further investigation. Is there a channel without publishing the code in this forum?

Regards,

Jens

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Highlighted
Teacher
Teacher
883 Views
Registered: ‎07-09-2009

Just had quick look at th ebook you have referenced, the gaisler one, which proudly notes "space applications".

The first thing I note is :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Sorry, any one that uses ieee.std_logic_arith and then says its for space, is not one that I would follow.

ieee.std_logic_arith  has many known and well documented faults,

take look here for some background.

https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/

https://vhdlguru.blogspot.com/2010/03/why-library-numericstd-is-preferred.html

http://computer-programming-forum.com/42-vhdl/dbc7768bd0da97fc.htm

etc

 

std_logic-arith is NOT a standard, but one orriginaly written by a company, and many people have made versions of it.

 

I'd strongly suggest if thats your source your referencing , that you get a better book,

 

This is getting dated,

   but is free and not bad

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

 

 

 

 

 

 

 

 

 

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Teacher
Teacher
879 Views
Registered: ‎07-09-2009

You need to

a) use a test bench to check functionality

b) check your timming constraints

c) post your code / and test bench as attatchments.

 

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Explorer
Explorer
873 Views
Registered: ‎06-25-2014

Unless you are a top 5 Xilinx customer I can't imagine you will be getting any joy from Xilinx to add Vivado support for this coding style. I would recommend you bite the bullet now and invest your time into the changes needed to get your code through the Vivado Synth engine.

By the way, the change may be pretty simple. (e.g. there is no problem having a separate combinational and clocked process, its "probably" more the use of variables that's messing it up)

NOTE: I have only quickly scanned your doc..

Keep in mind ISE is a very old tool that had LOADS of extra bits bolted on during its history to support all sorts of obscure coding styles that tier 1 customers insisted on having to win big $$$$ business etc. Vivado was purposely coded from the ground up.
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816 Views
Registered: ‎06-18-2014

@andrewlanI've found already a code-change to get my code correctly through vivado. However, my hope is that Xilinx will analyze the issue to improve the synthesis tool.

@drjohnsmithI use the principles of the Gaisler-style but I dont use this style letter by letter. E.g. I use only IEEE-packages. std_logic_arith std_logic_(un)signed do not belong to them. Style is always a topic of endless debates. I expect that a synthesis tool translates different styles.

It does not make sense to require a third time to run a testbench and to change constraints if this topic is already discussed.

Regards,

Jens

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Highlighted
Teacher
Teacher
794 Views
Registered: ‎07-09-2009

From what I remeber,

you have refised to share your full code as an attatchement,

you have refused to share your test bench to prove that the multipel styles are the same as you state

Peer review is a key stone of enginering,

In conclusin, you make un substantiated claims

So there is not much more we can do..

 

 

have a good day

 

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Explorer
Explorer
789 Views
Registered: ‎06-25-2014

Well, my only suggestion at this point is for you to look around other posts for the more active Xilinx employees and add a post below this one asking direcly for them to take your code, decide it's a tools issue and fix it. (i.e. @xilinxPerson123)

 

You never know, you may get lucky! :)

 

 

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Teacher
Teacher
779 Views
Registered: ‎07-09-2009

please refer to this very early post in this forum thread.

"

Kindly check behavioral simulation and post-synthesis functional simulation to see if you are getting correct functionality as per your expectations or not. If you are getting the wrong functionality then provide that specific signal name/cell name to evaluate it further.

Regards,
hemangd
 
"
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Scholar
Scholar
772 Views
Registered: ‎08-01-2012

I would agree this is a synth bug with vivado, as the two peices of code appear functionally identical (but this assumes the correct context - maybe a full code example would help prove it). It is likely to do with how vivado works with variables.

The Gaisler style is a very old style intended for a time when synthesis tools were pretty limited and needed the separation of combinatorial and registers logic. It was written about 20 years ago. It relys on the two process style that has generally fallen out of favor.

That aside, Vivado should really work with this....

 

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Explorer
Explorer
771 Views
Registered: ‎06-25-2014

@drjohnsmithAhhh, I missed that post! (I came in a bit late!) :)

 

Well there you go @jens.schoenherr, you have been told by a Xilinx person what to do next. 

 

 

Highlighted
745 Views
Registered: ‎06-18-2014

@hemangdDo you as a moderator know how to contact a Xilinx employee? The aim of my post is to help Xilinx to analyze this issue. There is no need to support me since I found a running workaround.

Regards,

Jens

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736 Views
Registered: ‎06-18-2014

@richardheadCould you recommend a style that is more abstract than the Gaisler one.

From the abstraction point of view there should be no big difference between one or the process styles. I prever the two-process one to have access to the register inputs.

Gaisler proposes the use of variables in the combinational part. For me this is very convinient because I change often between VHDL and C and the specific semantics of the signal assignment in VHDL seems to be error prone.

Regards,

Jens

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Scholar
Scholar
705 Views
Registered: ‎08-01-2012

@jens.schoenherr 

A breif description: https://vhdlwhiz.com/n-process-state-machine/

The current thinking is that single (synchronous) process is better to get into the habit of using as you can never create unintended latches. But it does have the side effect that all outputs are registered and you'll need separate process/in line assignements for non-registerd outputs - AXI being the most common culprit.

But all styles ultimately produce the same hardware and should be able to give the same results.

THe most important thing is well documented and tested code, ideally with self checking testbenches that actually cover a decent/all of the cases.