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Explorer
Explorer
4,307 Views
Registered: ‎12-02-2012

Synthesis not connecting input ports to output ports

I am using Vivado 2016.2 and have a design where I have an input being directly connected to the output port. Vivado however will not synthesize that direct connection, instead treating the input port as if it was not connected to anything, requiring that I put a flipflop in between the two. Is this a known behavior with the toolchain or something?

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Guide
Guide
4,304 Views
Registered: ‎01-23-2009

Re: Synthesis not connecting input ports to output ports

There is no reason the tools cannot do this (assuming you recognize that this connection is unidirectional - from an input (through an IBUF) to an output (through an OBUF).

 

If it is refusing to do so, this is most likely a bug in your code (or possibly a bug in the tool)...

 

Avrum

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Explorer
Explorer
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Registered: ‎12-02-2012

Re: Synthesis not connecting input ports to output ports

These are entirely internal and are not connected to pins.
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Guide
Guide
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Registered: ‎01-23-2009

Re: Synthesis not connecting input ports to output ports

So you are talking about a sub-module of your design, where an input goes directly to an output?

 

That too is legal (but odd). However, if you have flatten_hierarchy = rebuilt, which is the default, the tool is able to do "things" with your hierarchy. For example, it is probably allowed to connect the driver of the input directly to the receiver of the output outside the module in question. If it does this, both the input and output would be unused (and hence the input would be ignored, and the output tied to ground).

 

Avrum

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Explorer
Explorer
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Registered: ‎12-02-2012

Re: Synthesis not connecting input ports to output ports

flatten_hierarchy is set to none. The code seems to be tripping up in a conditional assignment to the output port wherein different parts of the input bus are placed in different bit locations of the output bus. Why the conditionalization is giving it so much trouble I have no idea, it looks like I'll have to refactor the checks to see if the logical chain is doing something unexpected.
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