02-09-2017 11:05 AM
I am using Vivado 2016.2 and have a design where I have an input being directly connected to the output port. Vivado however will not synthesize that direct connection, instead treating the input port as if it was not connected to anything, requiring that I put a flipflop in between the two. Is this a known behavior with the toolchain or something?
02-09-2017 11:14 AM - edited 02-09-2017 11:14 AM
There is no reason the tools cannot do this (assuming you recognize that this connection is unidirectional - from an input (through an IBUF) to an output (through an OBUF).
If it is refusing to do so, this is most likely a bug in your code (or possibly a bug in the tool)...
02-09-2017 11:18 AM
So you are talking about a sub-module of your design, where an input goes directly to an output?
That too is legal (but odd). However, if you have flatten_hierarchy = rebuilt, which is the default, the tool is able to do "things" with your hierarchy. For example, it is probably allowed to connect the driver of the input directly to the receiver of the output outside the module in question. If it does this, both the input and output would be unused (and hence the input would be ignored, and the output tied to ground).
02-09-2017 11:39 AM