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Adventurer
Adventurer
875 Views
Registered: ‎02-08-2016

Synthesis of dcp - elimination of redundant clocks

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Hi,

 

I am trying to speed up synthesis of large design for ASIC to FPGA application. Using verilog.

 

I have presynthesized one large block, the "Core|" using the OOC synth flow. I then read the Core.dcp file into the main design.

 

There are a number of clocks in the Core module. Some of these are redundant, as they are only used for ASIC test, e.g. test_clk_x.

 

If I synthesize the Core module OOC , then the test_clk_x and all parts of its logic cone are build into the netlist. However when the Core.dcp is synthesised as part of main design, test_clk_x == GND at top level. 

 

Will the top level synthesis process or subsequent OPT process successfully eliminate the redundant logic?

 

Thanks SImon

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Xilinx Employee
Xilinx Employee
1,246 Views
Registered: ‎01-05-2017

Re: Synthesis of dcp - elimination of redundant clocks

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HI Simon,

 

After synthesis, the opt_design phase is usually run and this will perform logic optimization and remove any redundant logic.

Refer to the section called Logic Optimization in UG904. It will explain what the various switches in the opt_design does.

 

Let me know if you have any follow up questions.

 

Cheers,

David

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2 Replies
Xilinx Employee
Xilinx Employee
1,247 Views
Registered: ‎01-05-2017

Re: Synthesis of dcp - elimination of redundant clocks

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HI Simon,

 

After synthesis, the opt_design phase is usually run and this will perform logic optimization and remove any redundant logic.

Refer to the section called Logic Optimization in UG904. It will explain what the various switches in the opt_design does.

 

Let me know if you have any follow up questions.

 

Cheers,

David

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Adventurer
Adventurer
849 Views
Registered: ‎02-08-2016

Re: Synthesis of dcp - elimination of redundant clocks

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Hi,

I suspected this is what happens in OPT.

Thanks for confirming.

Thanks for the prompt support.
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