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Observer
Observer
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Registered: ‎07-06-2009

Synthesis of parameterised components using generics and maths (VHDL/XST)

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Hi,

 

Apologies if this has been covered elsewhere, I've not been able to find it. I hope I'm posting in the right place, too!

 

I'm designing parametric components that depend on generic values given during instantiation of the component. Some components run these generics through some maths to configure logic, etc.

 

My question is this: do synthesis tools (in my case XST) calculate these values before implementation? I.e. since the generics' values are known at instantiation, are all the numeric values calculated to give static values, or will the FPGA perform the maths?

 

For example, suppose I have a parametric component with a std_logic_vector output whose width depends upon the log-2 of a generic. The log-2 of the number is calculated with a function in a package that I wrote. When I instantiate, the generic is given a value - lets say 4. When this is synthesised, will the tool calculate this as 2 and instantiate the component with an output width 2, or will it synthesise the function and perform the calculation at run-time?

 

I ask because I don't want to implement a load of maths that doesn't need to be run on the FPGA but at instantiation. I imagine the tool does perform the calculation since this kind of thing happens in programming languages (5-3 is performed at compile-time rather than run-time, for example).

 

I hope this makes sense!

 

Many thanks,

 

Tom

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Historian
Historian
5,351 Views
Registered: ‎02-25-2008

Re: Synthesis of parameterised components using generics and maths (VHDL/XST)

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tom_o wrote:

Hi,

 

Apologies if this has been covered elsewhere, I've not been able to find it. I hope I'm posting in the right place, too!

 

I'm designing parametric components that depend on generic values given during instantiation of the component. Some components run these generics through some maths to configure logic, etc.

 

My question is this: do synthesis tools (in my case XST) calculate these values before implementation? I.e. since the generics' values are known at instantiation, are all the numeric values calculated to give static values, or will the FPGA perform the maths?

 

For example, suppose I have a parametric component with a std_logic_vector output whose width depends upon the log-2 of a generic. The log-2 of the number is calculated with a function in a package that I wrote. When I instantiate, the generic is given a value - lets say 4. When this is synthesised, will the tool calculate this as 2 and instantiate the component with an output width 2, or will it synthesise the function and perform the calculation at run-time?

 

I ask because I don't want to implement a load of maths that doesn't need to be run on the FPGA but at instantiation. I imagine the tool does perform the calculation since this kind of thing happens in programming languages (5-3 is performed at compile-time rather than run-time, for example).

 

I hope this makes sense!

 

Many thanks,

 

Tom


Generics are, of course, constant at elaboration time. Any function that uses a generic and returns a constant will be computed at elaboration time and will be a constant after synthesis completes.

 

-a

----------------------------Yes, I do this for a living.

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Historian
Historian
5,352 Views
Registered: ‎02-25-2008

Re: Synthesis of parameterised components using generics and maths (VHDL/XST)

Jump to solution

tom_o wrote:

Hi,

 

Apologies if this has been covered elsewhere, I've not been able to find it. I hope I'm posting in the right place, too!

 

I'm designing parametric components that depend on generic values given during instantiation of the component. Some components run these generics through some maths to configure logic, etc.

 

My question is this: do synthesis tools (in my case XST) calculate these values before implementation? I.e. since the generics' values are known at instantiation, are all the numeric values calculated to give static values, or will the FPGA perform the maths?

 

For example, suppose I have a parametric component with a std_logic_vector output whose width depends upon the log-2 of a generic. The log-2 of the number is calculated with a function in a package that I wrote. When I instantiate, the generic is given a value - lets say 4. When this is synthesised, will the tool calculate this as 2 and instantiate the component with an output width 2, or will it synthesise the function and perform the calculation at run-time?

 

I ask because I don't want to implement a load of maths that doesn't need to be run on the FPGA but at instantiation. I imagine the tool does perform the calculation since this kind of thing happens in programming languages (5-3 is performed at compile-time rather than run-time, for example).

 

I hope this makes sense!

 

Many thanks,

 

Tom


Generics are, of course, constant at elaboration time. Any function that uses a generic and returns a constant will be computed at elaboration time and will be a constant after synthesis completes.

 

-a

----------------------------Yes, I do this for a living.

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Observer
Observer
4,584 Views
Registered: ‎07-06-2009

Re: Synthesis of parameterised components using generics and maths (VHDL/XST)

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Perfect, thanks very much for that :)
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