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hwlee
Visitor
Visitor
816 Views
Registered: ‎12-20-2020

Synthesis of real type values is not supported

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Hi, when I try to synthesize the XADC.v code from Xilinx in ISE 14.5, it shows the error message.

 

"ERROR:HDLCompiler:812 - Line 215: Synthesis of real type values is not supported."

 

Any idea to solve this? or just replace the 'real' data type?

 

Thanks in advance.

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kdeshwal
Xilinx Employee
Xilinx Employee
547 Views
Registered: ‎11-12-2019

Hi @hwlee ,

Real data type is not synthesizable data type in Vivado.
Refer link for details - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf#page=236

Thanks,
Kuldeep

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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

Simply replace the real data type. Use reg instead.

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drjohnsmith
Teacher
Teacher
708 Views
Registered: ‎07-09-2009

I don't know this XADC.V code you refer to.

   is it supplied by Xilinx ?

 

BTW: Why 14.5 ? 

   What OS you running on ?

 

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kdeshwal
Xilinx Employee
Xilinx Employee
548 Views
Registered: ‎11-12-2019

Hi @hwlee ,

Real data type is not synthesizable data type in Vivado.
Refer link for details - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf#page=236

Thanks,
Kuldeep

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kdeshwal
Xilinx Employee
Xilinx Employee
501 Views
Registered: ‎11-12-2019

Hi @hwlee ,

Please let us know if the query is resolved or you have any follow-up query.   

Thanks,
Kuldeep

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hwlee
Visitor
Visitor
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Registered: ‎12-20-2020

Hi, yes. The XADC.v code is supplied by Xilinx.

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hwlee
Visitor
Visitor
469 Views
Registered: ‎12-20-2020

Thank you.

The problem has solved by not synthesize the XADC.v code. Instead, copy over the XADC instantiation template from language template panel, and paste in inside the ADC top level module code (which you create yourself) with all ports declared which corresponding to the ports available from XADC instantiation template. 

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hwlee
Visitor
Visitor
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Registered: ‎12-20-2020

Thank you, the problem has solved. 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

@kdeshwal

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