UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mbence76
Visitor
220 Views
Registered: ‎01-18-2019

Synthesis of the IFF event qualifier

Jump to solution

Hi there,

Can someone please shed some light on the difference between the two code structures below?  I am puzzled.

always @ (posedge clk iff datavalid) begin
...
end

This worked perfect in simulation, but not in real life, nor was the integerated logic analizer (ILA) showing anything promising. Actually ILA was showing total nonsense.

(I was actually trying to save power with the iff event qualifier, hoping it would use the CE (clock enable) inputs of the FFs.)

Then I changed it to the code below and now it works:

always @ (posedge clk) begin
if (datavalid) begin
..
end     //  for if
end    // for always

What is it about the iff  that I should know better?

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
109 Views
Registered: ‎03-16-2017

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi @mbence76,

 

I have filed a CR (Change Request) with the development on this issue. If this construct is not supported (as per UG 901) then tool should throw a message. They may make necessary changes in upcoming Vivado versions.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
9 Replies
Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎05-22-2018

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi @mbence76,

From my thinking, IFF is not a supported synthesizable construct in Vivado Synthesis.

Thanks,

Raj.

Visitor mbence76
Visitor
170 Views
Registered: ‎01-18-2019

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi Raj,

yes, you must be right, but the real question is now: 

how come that my Vivado synthesizer did synthesize, did implement, dit generate a bitstream file (when the RTL source file was using IFF) ?

There was no "unsupported IFF construct" message or "synthesis failed" message. :-(

Have a nice day!

Miklos

 

0 Kudos
Moderator
Moderator
158 Views
Registered: ‎03-16-2017

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi @mbence76,

>>This worked perfect in simulation, but not in real life.

What do you mean by this ? Please elaborate.

 

And share the synthesis log file to evaluate when you were using IFF event qualifier.

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Visitor mbence76
Visitor
148 Views
Registered: ‎01-18-2019

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi hemangd,

>>This worked perfect in simulation, but not in real life.

>What do you mean by this ? Please elaborate.

The FPGA panel received bytes thru SPI from an MCU panel and sent back bytes to the MCU thru the same SPI. A Putty terminal window showed that the bytes from the FPGA were nonsense  (when the FPGA image was created from an RTL source containing IFF). Simulation revealed no difference in behavior between the IFF and the  if(datavalid) begin...end   structure.

 

>And share the synthesis log file to evaluate when you were using IFF event qualifier.

I have re-written the code since then way too many times, but created a brand new one-file project to recreate the phenomena. Here it is, please try it in Vivado 2018.2, under Win10.  It compiles without an error, without a warning.

`timescale 1ns / 1ps

module topmodule_t(
    input        clk,
    input        i_data,
    output logic o_data
    );
    
logic[2:0] cnt = 0;
logic       dv = 0;
    
always @ (posedge clk) begin
    if (cnt==0) dv <= 1;
    else        dv <= 0;   
    cnt <= cnt + 1;
end    
    
always @ (posedge clk iff dv) begin
    o_data <= i_data;
end

endmodule

 

0 Kudos
Scholar richardhead
Scholar
140 Views
Registered: ‎08-01-2012

Re: Synthesis of the IFF event qualifier

Jump to solution

Im going to be awkward here, and point out the simple answer is that "IFF" is not listed as a supported SV feature in the synthesis user guide (UG901):

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf

Secoondly, the main difference is that using iff really implies clock gating, rather than a clock enable, and so would never be supported in an FPGA as clock gating is definitely not recommended.

Here is post from stack exchange baically asking the same as you:

https://electronics.stackexchange.com/questions/177069/is-event-control-iff-in-systemverilog-the-same-like-clock-gating

TL:DR: Its a clock gating construct - dont use it unless you really want a gated clock.

0 Kudos
Visitor mbence76
Visitor
120 Views
Registered: ‎01-18-2019

Re: Synthesis of the IFF event qualifier

Jump to solution
Yes, thank you, I have given up using IFF. However the other question, as to why the synthesizer does not report IFF as an "unsupported feature", still puzzles me. Please see my previous post. Miklos
0 Kudos
Moderator
Moderator
110 Views
Registered: ‎03-16-2017

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi @mbence76,

 

I have filed a CR (Change Request) with the development on this issue. If this construct is not supported (as per UG 901) then tool should throw a message. They may make necessary changes in upcoming Vivado versions.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Moderator
Moderator
76 Views
Registered: ‎03-16-2017

Re: Synthesis of the IFF event qualifier

Jump to solution

Hi @mbence76,

As per the discussion with the developement, Vivado 2018.3 supports IFF event qualifier and hence synthesized design shows clock gating with AND gate (LUT). 

Hence, UG 901 will be updated according to it.

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Visitor mbence76
Visitor
62 Views
Registered: ‎01-18-2019

Re: Synthesis of the IFF event qualifier

Jump to solution
Wow, that is good news. I am not sure about the delay of the clock gating AND gate (LUT), but I am sure Xilinx knows what they are doing. :)
0 Kudos