08-08-2019 07:42 AM
Main question is in the subject line itself. I am using Vivado 2018.3.
When I run the Open Elaborated Design I get a failure.
ERROR: Top module empty or no top module found. 940 Infos, 138 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
But please see the SS where the top modules are clearly assigned and inside its the complete hierarchy of sub-modules is also present.
Any ideas why I am getting this error?
08-09-2019 01:05 AM
Could you attach the log files of the failed elaboration run and passing synthesis run?
08-09-2019 01:12 AM
08-09-2019 01:33 AM - edited 08-09-2019 01:34 AM
I know where to find the synth log but where should I look for a log of the 'Open Elaborated Design'?
All that I have is some o/p at the TCL console and I don't see any error message.Please see the console o/p in the txt file attached.
Note that whatever Warning messages you see below are all from Xilinx MIG IP Core.
08-09-2019 02:41 AM
Does Synthesis run pass?
Could you also provide the Synthesis run log?
08-09-2019 02:49 AM - edited 08-09-2019 02:52 AM
Yes synthesis passes with some Warnings (not critical warning). I would also want to add that the design has also been sucessfully Implemented and tested on an Artix7 FPGA.
Would it make sense for you to analyze a passing synth log file?
What is the subtle dependency/difference b/w Elaborate and synthesis (I know that constraints and library transformations are not applied during Elaboration) that can lead to an error like this?
08-09-2019 03:21 AM
Just hope to get some clue by comparing the two logs.
Elaboration is kind of the first step of Synthesis.
If the top level has something wrong in Elaboration, the same thing should also happen in Synthesis.
What is your purpose of opening the Elaborated design?
As Synthesis passes, you can open synthesized design for your analysis.
If you don't mind, please provide the synthesis log for investigation.
08-12-2019 02:01 AM
Hi @gin_xil ,
Which Vivado version are you using?
Please check that two things. 1. Make sure there are no syntax errors in your design sources. 2. Make sure there are no missing source files in your design sources.
08-14-2019 12:21 AM - edited 08-14-2019 12:22 AM
08-14-2019 01:28 AM
Hi @gin_xil ,
Is it possible to share the archived project or testcase to reproduce this issue at my end ? If yes, then i will send ezmove ftp through which you can provide it.
08-14-2019 02:15 AM
08-14-2019 03:40 AM
What if you remove -rtl_skip_ip option?
What is your purpose of using this option?
08-14-2019 04:48 AM
Hi @gin_xil ,
Which OS version are you using?
And can you try to overcome this critical warnings and then run synthesis directly?
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'slot_gmii_rx_fifo'. The XDC file c:/Work/elog/fpga_a7/sources/ip2/slot_gmii_rx_fifo/slot_gmii_rx_fifo.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'slot_gmii_rx_fifo'. The XDC file c:/Work/elog/fpga_a7/sources/ip2/slot_gmii_rx_fifo/slot_gmii_rx_fifo_clocks.xdc will not be read for any cell of this module.
08-19-2019 04:44 AM
I am using Win7 SP1.
Well that gmii_rx_fifo is being instiantiated on the basis of some generic. I can securely say that it does not affect the Impl stage.
However for this problem, I will resolve it and observe what happens.