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Adventurer
Adventurer
212 Views
Registered: ‎01-19-2018

Synthesis passes but Open Elaborated Design fails, why?

Main question is in the subject line itself. I am using Vivado 2018.3.

When I run the Open Elaborated Design I get a failure.

ERROR: Top module empty or no top module found.
940 Infos, 138 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details

But please see the SS where the top modules are clearly assigned and inside its the complete hierarchy of sub-modules is also present.

Untitled.png

Any ideas why I am getting this error?

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13 Replies
Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎05-14-2008

Re: Synthesis passes but Open Elaborated Design fails, why?

Could you attach the log files of the failed elaboration run and passing synthesis run?

-vivian

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Observer larshb
Observer
157 Views
Registered: ‎08-30-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

It is impossible to say without your log, but from my experience a usual suspect is mismatched array sizes. I can see you are mixing VHDL with Verilog. This might be part of the reason why synthesis works, but not elaboration.
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Adventurer
Adventurer
145 Views
Registered: ‎01-19-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

I know where to find the synth log but where should I look for a log of the 'Open Elaborated Design'?

All that I have is some o/p at the TCL console and I don't see any error message.Please see the console o/p in the txt file attached.

Note that whatever Warning messages you see below are all from Xilinx MIG IP Core.

 

 

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Xilinx Employee
Xilinx Employee
139 Views
Registered: ‎05-14-2008

Re: Synthesis passes but Open Elaborated Design fails, why?

Does Synthesis run pass?

Could you also provide the Synthesis run log?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Adventurer
Adventurer
134 Views
Registered: ‎01-19-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

@viviany,

Yes synthesis passes with some Warnings (not critical warning). I would also want to add that the design has also been sucessfully Implemented and tested on an Artix7 FPGA.

Would it make sense for you to analyze a passing synth log file?

What is the subtle dependency/difference b/w Elaborate and synthesis (I know that constraints and library transformations are not applied during Elaboration) that can lead to an error like this?

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Xilinx Employee
Xilinx Employee
126 Views
Registered: ‎05-14-2008

Re: Synthesis passes but Open Elaborated Design fails, why?

Just hope to get some clue by comparing the two logs.

Elaboration is kind of the first step of Synthesis.

If the top level has something wrong in Elaboration, the same thing should also happen in Synthesis.

What is your purpose of opening the Elaborated design?

As Synthesis passes, you can open synthesized design for your analysis.

If you don't mind, please provide the synthesis log for investigation.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Moderator
Moderator
85 Views
Registered: ‎03-16-2017

Re: Synthesis passes but Open Elaborated Design fails, why?

Hi @gin_xil ,

Which Vivado version are you using? 

Please check that two things. 1. Make sure there are no syntax errors in your design sources. 2. Make sure there are no missing source files in your design sources. 

 

Regards,
hemangd

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Adventurer
Adventurer
71 Views
Registered: ‎01-19-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

@vivianyThe synth log as well.

 

@hemangdno problems with <1> and <2>.

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Moderator
Moderator
60 Views
Registered: ‎03-16-2017

Re: Synthesis passes but Open Elaborated Design fails, why?

Hi @gin_xil ,

Is it possible to share the archived project or testcase to reproduce this issue at my end ? If yes, then i will send ezmove ftp through which you can provide it.

Regards,
hemangd

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Adventurer
Adventurer
50 Views
Registered: ‎01-19-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

@viviany @hemangd ,

Sorry can't share the project or its test case.

Have already provided the elaborate log and synthesis log. Can't any info be derived from them?

 

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Xilinx Employee
Xilinx Employee
44 Views
Registered: ‎05-14-2008

Re: Synthesis passes but Open Elaborated Design fails, why?

What if you remove -rtl_skip_ip option?

What is your purpose of using this option?

-vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Moderator
Moderator
36 Views
Registered: ‎03-16-2017

Re: Synthesis passes but Open Elaborated Design fails, why?

Hi @gin_xil ,

Which OS version are you using? 

And can you try to overcome this critical warnings and then run synthesis directly?

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'slot_gmii_rx_fifo'. The XDC file c:/Work/elog/fpga_a7/sources/ip2/slot_gmii_rx_fifo/slot_gmii_rx_fifo.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'slot_gmii_rx_fifo'. The XDC file c:/Work/elog/fpga_a7/sources/ip2/slot_gmii_rx_fifo/slot_gmii_rx_fifo_clocks.xdc will not be read for any cell of this module.

Regards,
hemangd

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Adventurer
Adventurer
8 Views
Registered: ‎01-19-2018

Re: Synthesis passes but Open Elaborated Design fails, why?

@hemangd,

I am using Win7 SP1.

Well that gmii_rx_fifo is being instiantiated on the basis of some generic. I can securely say that it does not affect the Impl stage.

However for this problem, I will resolve it and observe what happens.

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