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1,218 Views
Registered: ‎04-14-2018

Synthesis problem - Multiple driven - Memory description

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Hi community! My name is Mauro Cipollone and this is my first post in the forums. Since a couple of years ago I've been developing an 8-bit Microcontroller with the following structure:

 

Structure.png

As you can see, it has a Harvard architecture. The Programmer's ports are connected to another module that enables me to connect mi PC to the microcontroller in order to download my assembly programs.

I started the development with an Atlys board (Digilent board with an Spartan-6) in ISE and this year I finally replaced my board for a Nexys 4 DDR (Digilent board too with an Artix-7) which enabled me to migrate the project to Vivado.

 

When I work with ISE I have no trouble implementing the project into the FPGA but recently I tried to synthesize and implement the same code in Vivado but I'm not being able to do it because of multiple driven issues. After many debbuging hours I realized that I don't have that problem if I shrink the size of the memories so they don't occupy more than 512 bits or, if I leave the memories as the only modules connected to the buses (besides the CPU). This is why I infer the problem could be solved describing the memories in some other way or modifying some parameters in the synthesizer options but I cannot find the right way...

 

I've attached the code from the memories:

- DataMem: Data memory (1Kx8).

- InstMem: Instruction memory (8Kx16).

 

I know that the sizes of my memories are quite big and I could achieve the same functionality with a Xilinx IP but I want my microcontroller to be pure VHDL and not to have vendors parts in the design...

 

I'll appreciate any ideas you may have. Thanks in advance!

 

Mauro

1 Solution

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1,219 Views
Registered: ‎02-12-2018

Re: Synthesis problem - Multiple driven - Memory description

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the problem is that you have bidirectional ports on your memory. std_logic_vector is a resolved type, using multiple drivers is not allowed. The implementation errors tell you which signals are driving the memory ports.

 

You have multiple condition to drive your tri-state buffer. Also, tri-state buffer cannot be synthesized in FPGA fabric.

6 Replies
1,193 Views
Registered: ‎02-12-2018

Re: Synthesis problem - Multiple driven - Memory description

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can you post the error message?

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1,165 Views
Registered: ‎04-14-2018

Re: Synthesis problem - Multiple driven - Memory description

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@theultimatesource wrote:

can you post the error message?


Of course! I didn't post it because I consider it a bit confusing. I attach you the following files:

- Frankie.vhd: Top entity of the design presented in the picture of my original post. It has InterruptController and Timer decoupled in order to simplify the design for debugging. I attached this files because that's where s_link3 and s_link3 are (referred in the log of the synthesis).

- CriticalWarnings_Synthesis.txt: Critical warnings thrown by the synthesizer, they refer to the Top.vhd (which contains Frankie.vhd and a couple of modules more) file but this just confuses you, the problem is inside Frankie... (I've made some tests with Frankie as the top entity of the design and I have the same problems).

- Log_Synthesis.txt: Inside this file you can see that it refers to s_link3 and s_link11 when it talks about the multiple driven issues.

- Errors_Implementation: Implementation errors which are related to the critical warnings.

 

Thank you for your help!

 

Regards

 

Mauro

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1,220 Views
Registered: ‎02-12-2018

Re: Synthesis problem - Multiple driven - Memory description

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the problem is that you have bidirectional ports on your memory. std_logic_vector is a resolved type, using multiple drivers is not allowed. The implementation errors tell you which signals are driving the memory ports.

 

You have multiple condition to drive your tri-state buffer. Also, tri-state buffer cannot be synthesized in FPGA fabric.

1,137 Views
Registered: ‎04-14-2018

Re: Synthesis problem - Multiple driven - Memory description

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@theultimatesource wrote:

the problem is that you have bidirectional ports on your memory. std_logic_vector is a resolved type, using multiple drivers is not allowed. The implementation errors tell you which signals are driving the memory ports.

 

You have multiple condition to drive your tri-state buffer. Also, tri-state buffer cannot be synthesized in FPGA fabric.


@thank you very much for your fast reply @theultimatesource. Unfortunately, I don't think that what you are saying is related to my problem... Obviusly using multiple drivers is never allowed but inout ports have the capability to support more than two signals connected at the same time if your code is never gonna have data collisions (because when some module pulls up or down the signal the rest present high impedance).

On the other hand, I know that the implementation error is telling me which signals drive the memory ports but what is strange is that when I shrink the memory the problem disappears. I don't want to seem stubborn but this is a code that I've implemented and downloaded into the FPGA many times before with ISE and an Spartan-6... Do you propose some way to modify my code in order to achieve the desired behaviour?

 

Thank you very much for your help.

 

Regards!

 

Mauro 

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1,125 Views
Registered: ‎02-12-2018

Re: Synthesis problem - Multiple driven - Memory description

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@mauro.cipollone,

 

You're welcome. The problem is that you are infering tri-state buffer. This is not possible in FPGA fabric. Only IO buffer support tri-state. Eventually, some synthesis tools are coming up with a "solution" for this but others don't. This is undesirable as it leads to unpredictable results among different tools (and designs).

 

It is recommended to replace inout ports into separate input and output ports in your entities. In order to find out why you are achieving different results by using less memory we need to observe the synthesis result. You can try to compare your resource utilization between both variants.

1,033 Views
Registered: ‎04-14-2018

Re: Synthesis problem - Multiple driven - Memory description

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@theultimatesource wrote:

@mauro.cipollone,

 

You're welcome. The problem is that you are infering tri-state buffer. This is not possible in FPGA fabric. Only IO buffer support tri-state. Eventually, some synthesis tools are coming up with a "solution" for this but others don't. This is undesirable as it leads to unpredictable results among different tools (and designs).

 

It is recommended to replace inout ports into separate input and output ports in your entities. In order to find out why you are achieving different results by using less memory we need to observe the synthesis result. You can try to compare your resource utilization between both variants.


@theultimatesource, I apologize for the delay of my answer, I've read a lot of articles and made several test with different bus connections possibilities in order to see which would be the most simple and effective solution for my problem.

First of all, you were right, the problem is the fact that I'm using inout ports and the synthesizer doesn't know how to resolve them without tri-state buffers. It's quite frustrating to have developed a big code which used to compile ok with ISE and find that now I have to modify it just because the synthesizer logic changed...

On the other side, the solution that I finally implemented was (besides separe data input and output buses) a multiplexer controlled by the address bus which connected the data_out signal of the peripheral that is going to be read to the data_input signal from the CPU (because several outputs talking to the same input logically will generate a multiple driven too). The enable, read_write, address and data_out signals from the CPU to the peripherals remained connected from the CPU to the peripherals.

So, well... I'll have to change a lot of code...

I leave the following links which helped me to understand the situation for anyone who experience the same problem I had:

Thank you very much for sharing your knowledge and your time!

 

Regards

 

Mauro

 

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