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1,016 Views
Registered: ‎12-17-2017

Synthesis problem that never ends

Hello, everyone,
I have a problem with synthesizing my model, I would even say that the problem may be related to VIVADO. Because when I synthesized my model two months ago, the synthesizing is done without any problem and in less than 30min. I would like to appreciate that I use System Generator for DSP. So, for the past two weeks, when I have been generating the VHDL code via system Generator, when I open the IDE project to synthesize in VIVADO, the synthesizing process takes an infinite time and never ends.

I thought maybe the problem was related to my model and I tried to synthesize a basic circuit like the one in the attachment.

When a Run Beheviral simulation I have prints screen in the attachment.

thank you in advance for your availability.

 

 

 

 

 

v1.png
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16 Replies
Xilinx Employee
Xilinx Employee
976 Views
Registered: ‎06-27-2018

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

Are you not able to synthesize this code too? To verify if the issue is design specific or not you can try synthesizing any Vivado example design. It could be a memory issue.

Thanks,

Chinmay

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938 Views
Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Good morning, everyone,


Thank you to everyone who had to take a look at my problem, and even more so to the Xilinx employee.
I followed your advice by synthesizing the example Base_Zynq_MPSoC, unfortunately I had the same problem, the synthesizing never ends.  Below is the screen printout and messages:

 

start_gui
create_project project_1 E:/demo/demo33/demo35/demo36/project_1 -part xczu9eg-ffvb1156-2-e
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
create_project: Time (s): cpu = 00:00:43 ; elapsed = 00:00:34 . Memory (MB): peak = 1165.496 ; gain = 372.699
set_property board_part xilinx.com:zcu102:part0:3.1 [current_project]
set_property target_language VHDL [current_project]
create_bd_design "Base_Zynq_MPSoC" -mode batch
Wrote  : <E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/Base_Zynq_MPSoC.bd>
Adding cell -- xilinx.com:ip:zynq_ultra_ps_e:3.1 - zynq_ultra_ps_e_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_99M
Adding cell -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding cell -- xilinx.com:ip:axi_bram_ctrl:4.0 - axi_bram_ctrl_0
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <Base_Zynq_MPSoC> from BD file <E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/Base_Zynq_MPSoC.bd>
open_bd_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1853.344 ; gain = 88.563
Wrote  : <E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/ui/bd_1f8d8c75.ui>
instantiate_example_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:18 . Memory (MB): peak = 1853.355 ; gain = 687.859
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 2
INFO: [BD 41-1662] The design 'Base_Zynq_MPSoC.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_awid'(17) to net 's00_couplers_to_xbar_AWID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_arid'(17) to net 's00_couplers_to_xbar_ARID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_awid'(17) to net 's01_couplers_to_xbar_AWID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_arid'(17) to net 's01_couplers_to_xbar_ARID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp0_bid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM0_FPD_BID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp0_rid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM0_FPD_RID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(12) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp1_bid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM1_FPD_BID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp1_rid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM1_FPD_RID'(17) - Only lower order bits will be connected.
VHDL Output written to : E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/synth/Base_Zynq_MPSoC.v
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_awid'(17) to net 's00_couplers_to_xbar_AWID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_arid'(17) to net 's00_couplers_to_xbar_ARID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_awid'(17) to net 's01_couplers_to_xbar_AWID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps8_0_axi_periph/xbar/s_axi_arid'(17) to net 's01_couplers_to_xbar_ARID'(16) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp0_bid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM0_FPD_BID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp0_rid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM0_FPD_RID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(12) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp1_bid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM1_FPD_BID'(17) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/maxigp1_rid'(16) to net 'zynq_ultra_ps_e_0_M_AXI_HPM1_FPD_RID'(17) - Only lower order bits will be connected.
VHDL Output written to : E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/sim/Base_Zynq_MPSoC.v
VHDL Output written to : E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/hdl/Base_Zynq_MPSoC_wrapper.v
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.1-0] Base_Zynq_MPSoC_zynq_ultra_ps_e_0_0:
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_99M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_bram_ctrl_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/ip/Base_Zynq_MPSoC_auto_ds_1/Base_Zynq_MPSoC_auto_ds_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m01_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/ip/Base_Zynq_MPSoC_auto_ds_0/Base_Zynq_MPSoC_auto_ds_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/ip/Base_Zynq_MPSoC_auto_pc_0/Base_Zynq_MPSoC_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/m00_couplers/auto_pc .
Exporting to file E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/hw_handoff/Base_Zynq_MPSoC.hwh
Generated Block Design Tcl file E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/hw_handoff/Base_Zynq_MPSoC_bd.tcl
Generated Hardware Definition File E:/demo/demo33/demo35/demo36/project_1/project_1.srcs/sources_1/bd/Base_Zynq_MPSoC/synth/Base_Zynq_MPSoC.hwdef
[Sun Jan 20 20:25:25 2019] Launched Base_Zynq_MPSoC_auto_ds_1_synth_1, Base_Zynq_MPSoC_xbar_0_synth_1, Base_Zynq_MPSoC_auto_ds_0_synth_1, Base_Zynq_MPSoC_auto_pc_0_synth_1, Base_Zynq_MPSoC_axi_gpio_0_0_synth_1, Base_Zynq_MPSoC_zynq_ultra_ps_e_0_0_synth_1, Base_Zynq_MPSoC_axi_bram_ctrl_0_0_synth_1, Base_Zynq_MPSoC_rst_ps8_0_99M_0_synth_1, Base_Zynq_MPSoC_blk_mem_gen_0_0_synth_1...
Run output will be captured here:
Base_Zynq_MPSoC_auto_ds_1_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_auto_ds_1_synth_1/runme.log
Base_Zynq_MPSoC_xbar_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_xbar_0_synth_1/runme.log
Base_Zynq_MPSoC_auto_ds_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_auto_ds_0_synth_1/runme.log
Base_Zynq_MPSoC_auto_pc_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_auto_pc_0_synth_1/runme.log
Base_Zynq_MPSoC_axi_gpio_0_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_axi_gpio_0_0_synth_1/runme.log
Base_Zynq_MPSoC_zynq_ultra_ps_e_0_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_zynq_ultra_ps_e_0_0_synth_1/runme.log
Base_Zynq_MPSoC_axi_bram_ctrl_0_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_axi_bram_ctrl_0_0_synth_1/runme.log
Base_Zynq_MPSoC_rst_ps8_0_99M_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_rst_ps8_0_99M_0_synth_1/runme.log
Base_Zynq_MPSoC_blk_mem_gen_0_0_synth_1: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/Base_Zynq_MPSoC_blk_mem_gen_0_0_synth_1/runme.log
[Sun Jan 20 20:25:26 2019] Launched synth_1...
Run output will be captured here: E:/demo/demo33/demo35/demo36/project_1/project_1.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 2003.074 ; gain = 138.656
reset_run Base_Zynq_MPSoC_auto_ds_0_synth_1
reset_run Base_Zynq_MPSoC_auto_pc_0_synth_1
reset_run Base_Zynq_MPSoC_axi_gpio_0_0_synth_1
reset_run Base_Zynq_MPSoC_zynq_ultra_ps_e_0_0_synth_1
reset_run Base_Zynq_MPSoC_axi_bram_ctrl_0_0_synth_1
reset_run Base_Zynq_MPSoC_rst_ps8_0_99M_0_synth_1
reset_run Base_Zynq_MPSoC_blk_mem_gen_0_0_synth_1
reset_run synth_1
reset_run Base_Zynq_MPSoC_auto_ds_1_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. PID not specified

reset_run Base_Zynq_MPSoC_xbar_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. PID not specified

And regarding memory, when the systems were working normally, I still have the following settings in screen print:

Thank you.

 

 

 

v1.png
v2.png
v3.png
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Moderator
Moderator
920 Views
Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

 

Turn off your antivirus temporarily and then create a new example design project in different directory/drive.

When you lunch a synthesis, Vivado copies two files (ISEWrap.sh and ISEWrap.js) into the project synthesis folder (i.e. project_1.runs\synth_1). If only ISEWrap.sh was present in synth_1 and ISEWrap.js not here or even in Vivado/script folder, then your antivirus is quarantining the ISEWrap.js file. 

Consult with your IT team as well regarding which files are getting quarantine by your antivirus. - I believe this could be the issue here. 

Regards,
hemangd

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908 Views
Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Once again hello,
I followed your instructions, I even went even further by completely uninstalling the antivirus. But the problem remains unchanged.

I also modify the backup paths not always change.


And I checked, both files are actually available in the synth_1 folder. Both files are available for all my projects. See screen print below:

thank you

 

v1.png
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Moderator
Moderator
895 Views
Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

As i suggested above, create a new project using example design in another drive (other than E drive) and check. Make sure your computer name (My Computer) name is in english letters only.

 

Run "report_environment -file <filepath>/env.txt" in tcl console and provide env.txt to evaluate. 

Also provide the Vivado.log from the project directory to check.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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883 Views
Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Thank you again,

But I didn't always have a solution, the synthesis still doesn't stop.
Below in attached files, the two files you requested.

With regard to the sentence below:
Make sure your computer name (My Computer) name is in english letters only.
I must admit, I don't understand.

I right clicked and replaced the name (Ordinateur) with (My Computer) and went further by changing the regional settings in Anglais (États-Unis). Not always change.
Thank you for your availability.

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Moderator
870 Views
Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

 

1. Have you tried a new project (example design) in C drive?

2.Remove space in between  Famile Bemelingue from the path  - APPDATA=C:\Users\Famille Bemelingue\AppData\Roaming  And then check if you face the same error or not.

Check this thread for more info. https://forums.xilinx.com/t5/Synthesis/Vivado-2017-4-elaboration-fail/td-p/823110

 

 

Regards,
hemangd

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Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Good morning, everyone,
After having tried all the above solutions without success, I found myself in the obligation to format my system.

Now I have another problem, other than synthesizing.
After installing the Systerm Generator, when I click on the icon on the desktop I get the message printed on the screen.

 

which means   (the application failed to start correctly (0xc0000007b))

Sans titre01.png

After several searches on the Internet, it appears that the problem is related to the version of Microsoft Visual C++ Redistributable 2015 (64bit).
The screenshot below shows the version of Microsoft Visual C++ Redistributable 2015 (64bit) that I used, but unfortunately there is not any day of change.

 

Sans titre02.png

 

So, I would like to know which versions of Microsoft Visual C++ Redistributable 2015 (64bit) are compatible with :
- Vivado_SDK_2017.2
- Vivado_SDK_2017.4
If possible links to download the different versions please.

thank you

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Moderator
Moderator
789 Views
Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

 

Please create a new thread for system generator issue. 

Is synthesis working now?

Microsoft redistributables 2015 (x64) is required.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Hi,

The systematization didn't work so I formatted my computer.

I know we need Microsoft redistributable 2015 (x64), but
please which version respectively for:
- Vivado_SDK_2017.2 and,
- Vivado_SDK_2017.4
thank you

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Moderator
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Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

 

Yes for both VIvado SDK 2017.2 and 2017.4 - redistributables 2015 (x64) is required.

Regards,
hemangd

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Registered: ‎12-17-2017

Re: Synthesis problem that never ends

Hello,

As shown in the red part of the screen print below, I used Microsoft Visual C++ Redistributable x64 version 14.0.242015, but it still doesn't work for both Vivado_SDK_2017.2 and Vivado_SDK_2017.4.

Sans titre02.png

So my question is what is the exact version of Microsoft Visual C++ Redistributable 2015 x64 to use.

Thank you. Thank you.

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Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @gabiandpaulain7526,

Create a new thread in installation board for this issue since it is related to system generator installation. So, community can help you better.

 

 

 

Regards,
hemangd

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Registered: ‎01-28-2018

Re: Synthesis problem that never ends

I have the same problem with a design containing 2 MIGs (VIVADO 2018.3 64 Bit, Board VCU108).

The design worked fine before. After some changes in some sub-modules the synthesis stucks at some point, showing CPU usages below 10%, most time between 1 and 5%.

I have tried to stop the antivirus tool, without success. Last time I started the synthesis at 6 in the evening and it has not finished right now (8 am).

The design-Run tab looks like on the image enclosed. Apparently some components terminated successfully, then the tool stucks at some component which cannot be identified.

Any solutions for this problem?

Norbert

 

 

SynthStuck1.jpg
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Registered: ‎01-28-2018

Re: Synthesis problem that never ends

Again we have a very, very annoying problem that causes me wasting a lot of time.

I completely removed vivado from my system and re-installed it. Without any success. The synthesis stucks at a very low CPU load.

Norbert

SynthStuck2.jpg
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Registered: ‎03-16-2017

Re: Synthesis problem that never ends

Hi @norbertreifschneider,

 

Create a new thread with your issue. So community can help you better.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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