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mahmoud_xilinx
Observer
Observer
830 Views
Registered: ‎08-11-2019

Synthesis problem when resetting a large array of registers

Hi everyone,
I'm developing a large design on VU5P (Virtex-7 Ultrascale+). There are 2 of 2 dimension array of "reg" in one module:

reg [2047:0] T1_flag [7:0],
                     T2_flag [7:0];

 

In previous version, I just initilized them and during the code I just set a single register as 0 or 1. And everything was ok (in synthesis and implement).

An snapshot of the synthesis report is as below, which shows normal quantity for LUTs of design:

ok.jpg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

But after adding a global reset for all these registers in a certain condition (as below:)

always @(posedge clk_in) begin : Global_reset
  if(A && B)
    for(ii=0; ii<8; ii=ii+1)
      for(jj=0; jj<2048; jj=jj+1)
        begin
          T1_flag[ii][jj] <= 0;
          T2_flag[ii][jj] <= 0;
        end

And when synthesis, the report changes as below:

nok.jpg

 

 

 

 

 

 

 

 

 

 

 

 

 

And synthesis works for a long time and finally, lack of resource is reported.

Accessing these registers is very limited and just in one process. Actually I have no idea to find the bug.

Can anyone help me?

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5 Replies
calibra
Scholar
Scholar
817 Views
Registered: ‎06-20-2012

Do you really need a register file ?
Why do you not use a BRAM?

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mahmoud_xilinx
Observer
Observer
799 Views
Registered: ‎08-11-2019

Hi @calibra ,

Actually BRAM is used for another purpose and also, final size of T1_flag and T2_flag registers can be up to 256K bit.

I may switch to BRAM for them. But anyway, the problem still exists. Why can't I reset the register bank?

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mahmoud_xilinx
Observer
Observer
791 Views
Registered: ‎08-11-2019

@calibra ,

The other reason I can't use BRAM is the Edge_detect process I need to do on T1_flag and T2_flag to find the first "1" or "0" in them, and using BRAM I need to waste several clock cycles to read them from Memory.

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viviany
Xilinx Employee
Xilinx Employee
730 Views
Registered: ‎05-14-2008

The long runtime is due to the large loop.

Is the final total resource utilization the expected number?

Do you have to reset those registers?

If removing reset is not an option, I suggest you reduce the size of the register array to small ones.

For example,

reg [255:0] T1_flag1 [7:0];

reg [255:0] T1_flag2 [7:0];

reg [255:0] T1_flag3 [7:0];

...

And the reset description can be as below so that you don't need nested loop.

if(A && B)
      for(jj=0; jj<255; jj=jj+1)
        begin
          T1_flag1[jj] <= 8'b00000000;
        end

-vivian

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mahmoud_xilinx
Observer
Observer
663 Views
Registered: ‎08-11-2019

@viviany ,

As I said, the final resource utilization is even more than all available resources in the chip.

 

Actually seems the problem is how to access the register banks not the size of arrays.

I mean if I reset the register banks with a variable index (Message_Counter is a variable counting incoming messages to the module) as below:

if(A && B)
  begin
      T1_flag[Message_counter] <= 2048'b0;
      T2_flag[Message_counter] <= 2048'b0;
  end

Then everything is ok, but if I access them directly, as below:

if(A && B)
  begin
      T1_flag[0] <= 2048'b0;
      T2_flag[0] <= 2048'b0;
  end

Then it goes to the bad state. I just tested with above blocks.

It means synthesis is sensitive to how to address them.


And in the process I'm going to reset them, everything is addressed with the "Message_counter" variable.
I will send the code to you to check if needed.

Regards,