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Registered: ‎06-08-2017

Synthesis seems to trim logic when it shouldn't

I've got a design that sends a bunch of serial data to program an LCD touchscreen. The data is held in an array, cmdarr. Each element of cmdarr is a 56 bit word. The module works most of the time, meaning the display does what I expect. But sometimes, seemingly at random, I compile a bitstream with a minor change to a version that just worked, and the display does not even turn on. If I put VIO on the last few bytes of data, then it works. And if I put (* DONT_TOUCH *) before the declaration of cmdarr the display works.

Any ideas why this might be happening? Could this be a bug in the synthesis tools in Vivado, or some bug or conflict in the code I've written?

Thank you.


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Xilinx Employee
Xilinx Employee
Registered: ‎05-14-2008

Though it works after adding "dont_touch", it doesn't mean the logics are trimmed before adding dont_touch. Have you checked if the corresponding logics exist in the post-synthesis netlist by opening the Synthesized design?

You can also comparing the connections in the netlist before and after adding dont_touch or VIO.

If this is not a logic issue, it is probably a timing issue. First try baselining your design to check if it is fully and correctly constrained. Please refer to UG949 for information about baselining.

It is worth comparing the timing on the paths that might be related to the HW failure in the designs with and without dont_touch or VIO. Check paths that have very small positive slacks like 0.00x ns.


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