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kinkeads
Adventurer
Adventurer
8,085 Views
Registered: ‎12-20-2010

Synthesis utilization graph reports incorrect DSP48 usage

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After successfully completing synthesis on my design, the Utilization Table in the Project Summary, under-reports the usage of DSP48 cores in my design.  However, the utilization report (Flow Navigator > Synthesis > Report Utilization) reports the correct usage.    My design is hierachial and it appears the Utilization Table did not count the DSP48s contained in 4 of the sub-modules that contain the cores.

 

The attached screen capture shows both reports.   The Utilization Table incorrectly shows 1087 DSP48s while the utilization reports correctly shows 2111 DSP48s. 

 

I'm using Vivado 2015.2

 

Capture.JPG

 

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vemulad
Xilinx Employee
Xilinx Employee
15,427 Views
Registered: ‎09-20-2012

Hi @kinkeads

 

This is expected behavior.

 

This is because the Synthesis utilization in the project summary window does not include the resource utilization of any instantiated DCP or any OOC module.

 

When you load the synthesized design, it loads the DCP or OOC module netlist too and hence the value differs.

 

You need to either refer to the post implementation utilization in the project summary window or open synthesized design and run "report utilization" manually to get the correct utilization.

 

Thanks,

Deepika.

 

.

Thanks,
Deepika.
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kinkeads
Adventurer
Adventurer
8,076 Views
Registered: ‎12-20-2010

Repost of the screen capture with the discrepencies circled in red.

 

 

Capture.JPG

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vemulad
Xilinx Employee
Xilinx Employee
15,428 Views
Registered: ‎09-20-2012

Hi @kinkeads

 

This is expected behavior.

 

This is because the Synthesis utilization in the project summary window does not include the resource utilization of any instantiated DCP or any OOC module.

 

When you load the synthesized design, it loads the DCP or OOC module netlist too and hence the value differs.

 

You need to either refer to the post implementation utilization in the project summary window or open synthesized design and run "report utilization" manually to get the correct utilization.

 

Thanks,

Deepika.

 

.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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vemulad
Xilinx Employee
Xilinx Employee
8,015 Views
Registered: ‎09-20-2012

Hi @kinkeads

 

If your query is answered, please close the thread by marking the answer in interest of other users.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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