01-06-2021 08:13 PM
I was reading "Generating Hardware Assertion Checkers" and it mentioned that Xilinx was able to covert Synthesizable Assertions into a checker. Is this still possible? How is this done?
02-14-2021 10:26 AM
02-18-2021 08:33 PM
Of course be warned that as of 2018.1 it is STILL buggy as all get-out.
process(Clk) if Clk'rising_edge then ... //some conditional state case if (not Rdy) then Report "Warning, bus error" Severity Warning; // actual bus error logic here ...
You would EXPECT this to only evaluate at run time in simulation and get IGNORED by compile time synthesis. However no. It unconditionally evaluates the Report keyword and actually puts a Warning in your log file.
You have to do BS work-arrounds like "Assert false Report ..." because even though a 'naked' Report is a sub-case of an Assert statement, the compiler treats them 100% differently and stupidly.