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gochango
Visitor
Visitor
516 Views
Registered: ‎06-12-2019

Synthesizable Assertion

I was reading "Generating Hardware Assertion Checkers" and it mentioned that Xilinx was able to covert Synthesizable Assertions into a checker. Is this still possible? How is this done?

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3 Replies
kdeshwal
Xilinx Employee
Xilinx Employee
384 Views
Registered: ‎11-12-2019

Hi @gochango ,

If you are concerned about VHDL assertion support, then yes these are supported and you need to enable them by running a tcl command. 
Refer AR#65415 for details.

Thanks,
Kuldeep

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bitjockey
Adventurer
Adventurer
324 Views
Registered: ‎03-21-2011

Of course be warned that as of 2018.1 it is STILL buggy as all get-out.

process(Clk)
if Clk'rising_edge then
    ...
    //some conditional state case
    if (not Rdy) then
        Report "Warning, bus error" Severity Warning;
        // actual bus error logic here
...

You would EXPECT this to only evaluate at run time in simulation and get IGNORED by compile time synthesis.  However no. It unconditionally evaluates the Report keyword and actually puts a Warning in your log file.

You have to do BS work-arrounds like "Assert false Report ..." because even though a 'naked' Report is a sub-case of an Assert statement, the compiler treats them 100% differently and stupidly.

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richardhead
Scholar
Scholar
305 Views
Registered: ‎08-01-2012

@bitjockey that bug is fixed in 2019.1. Runtime assertions are ignored from synthesis,  and only static elaboration ones are checked.

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