02-10-2019 04:56 AM
usually I use Xilinx FPGAs but from time to time I also have to use Lattice FPGAs, in this case for a project where the customer asked for Lattice iCE40. I mainly use Verilog HDL.
To be able to use Xilinx as well as Lattice I want to make my source code very generic. This works already but for every file in which I use IPs I have to keep two files, one for Xilinx, one for Lattice.
What I want to do is the following, but I don't know if this is good style.
#ifdef XILINX // Xilinx module instantiation #else if LATTICE
// Lattice module instantiation
Does someone of you already use such a construct to synthesize for two FPGA vendors? Are there predefined compiler defines which I can use? Else I would think about defining a global define for the whole project in Vivado toolchain and doing exactly the described method above.
Thanks for helping!
02-10-2019 05:30 AM
02-10-2019 06:34 AM
Did you face any errors after using this method?
I am not sure it will work or not after adding lattice module instantiation. But, give it a try with it since ifdef method is supported.
02-10-2019 06:38 AM
Hi, @sebastian_z ,
I have seen the method you mentioned used properly in my customer's real design.
I think the method is reasonable.
02-10-2019 08:13 AM - edited 02-10-2019 08:17 AM
Thank you very much for your answer. I tried it with the ifdef because I think it is reasonable too, but I do have an error message which I received 6 months ago and then stopped trying. But now I need that solution.
The problem is that as soon as I add the ifdef around the module instantiation I get the error message that the module is not found. As soon as I remove the ifdef, all steps go fine and at the end I do have a valid bitfile.
So please have a look at the error message.
02-11-2019 06:44 AM
Using report_compile_order command to check whether the define.v(the header file with macro define) is compiled earlier than your source code with `ifdef.
02-11-2019 07:05 AM
You might add a $display in there with some text to show that the `ifdef was used ... or not.
Alternatively, it might be better to use parameters and generate statements.
For instance set the parameters at the top level module, something like
module sebastians_scalable_module #(
parameter ISLATTICE = 0
); ... generate if (ISLATTICE == 1) begin RTL to adapt to lattice primitive Lattice primitive end endgenerate generate if (ISLATTICE == 0) begin RTL to adapt to xilinx primitive xilinx primitive end endgenerate
So that's another option that allows use of generics (VHDL) / parameters (vlog) in a hierarchical deisgn...
02-11-2019 10:34 PM
thank you very much. I thought about that method too and I really like it. Just one question about that: is it possible to use global verilog_defines as described above and not parameters? The advantage of defines would be that I don't need to add them to the generic list (VHDL) / parameter list (Verilog).